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CoWoS-S Packaging: Silicon Interposers for AI and HPC

September 21st, 2026

CoWoS-S packaging places logic dies and high-bandwidth memory (HBM) side by side on a silicon interposer. Fine metal wiring connects the dies across that interposer, while through-silicon vias connect it vertically to a separate package substrate. This arrangement supplies the dense, short memory connections needed by AI accelerators and high-performance computing systems.

Conceptual CoWoS-S package with logic and HBM above a continuous silicon interposer

What Is CoWoS-S Packaging?

CoWoS-S is TSMC’s silicon-interposer version of Chip-on-Wafer-on-Substrate packaging: the “S” identifies the silicon interposer that carries the die-to-die wiring.

Within the CoWoS semiconductor packaging family, its distinguishing feature is a continuous silicon interposer beneath the top dies. The logic and HBM are separate components connected on this shared routing platform, rather than one monolithic chip. HBM itself contains vertically stacked memory dies, but the side-by-side arrangement of logic and memory on the interposer is commonly described as 2.5D integration.

TSMC develops the package technology; the system board sits at a different manufacturing level. Our introduction to TSMC’s manufacturing technologies explains that broader context.

What Is Inside a CoWoS-S Package?

A CoWoS-S package contains logic dies and HBM above a silicon interposer, fine die-attachment connections at their interfaces, and a package substrate beneath the interposer.

Part Position Function
Logic die Above the interposer Processes data and controls memory access
HBM stack Beside the logic die Provides wide-interface, high-bandwidth memory
Microbumps Between top dies and interposer Connect die pads to interposer wiring
Silicon interposer Below logic and HBM Routes dense connections between dies
Through-silicon vias (TSVs) Through the interposer thickness Carry connections to its underside
Package substrate Below the interposer Redistributes connections toward board-facing terminals

The CoWoS S silicon interposer is primarily an interconnect platform, not an additional processor. It can also incorporate passive functions such as integrated capacitance. The silicon interposer, organic package substrate, and system PCB are therefore three distinct structures—not interchangeable names for the same board.

Underfill and the thermal assembly complete important mechanical and heat-transfer functions. Their materials depend on the qualified package design; a conceptual cross section does not specify an actual lid, thermal-interface material, or assembly thickness.

How Does CoWoS-S Connect Logic Dies and HBM?

Logic-to-HBM signals travel from a die’s pads through microbumps, laterally along the interposer’s metal wiring, and through another set of microbumps into the memory interface.

Lateral logic-to-HBM routing and vertical TSV connections to the package substrate

This lateral memory path is different from the vertical path through interposer TSVs toward the package substrate. An HBM data signal does not have to travel down to the system PCB and back up to the neighboring memory stack. Keeping many connections within the package supports a wide memory interface without routing that interface across the board.

  • Connection density: fine interposer wiring accommodates many parallel signal connections in a small area.
  • Shorter paths: adjacent die placement reduces the distance compared with off-package memory routing, although actual delay and loss depend on the layout.
  • Matched interfaces: logic memory controllers, HBM generation, pad maps, and package routing must work together. An interposer alone does not set bandwidth.

CoWoS S bump pitch refers to center-to-center spacing at a specified bump interface. It must not be confused with TSV pitch, metal line spacing, or board-level BGA pitch. For example, a hypothetical 40 ”m pitch with 20 ”m-wide pads leaves a nominal 20 ”m edge gap; those illustrative dimensions are not a CoWoS-S specification.

Microbump, TSV, and BGA pitches refer to different package interfaces

How Is a CoWoS-S Package Manufactured?

The CoWoS-S process flow prepares the silicon interposer, attaches the logic and memory dies to it, and integrates the resulting assembly with a package substrate.

  1. Design the interconnect platform: coordinate die locations, HBM interfaces, routing layers, TSVs, and power connections.
  2. Fabricate the interposer: form fine metal interconnects and the required through-silicon connections. Large designs may use lithographic stitching across exposure fields.
  3. Prepare the backside connections: thinning and backside processing provide access to the interposer’s vertical interconnects.
  4. Attach the top dies: align the logic and HBM interfaces with the interposer connections and form the die joints, with appropriate mechanical reinforcement.
  5. Complete and verify the package: integrate the package substrate and thermal structure, then check electrical operation and package reliability.

These are public functional stages, not a recipe for TSMC’s proprietary production line. Bonding temperatures, process ordering, tolerances, and inspection limits require the applicable qualified process documentation.

Reliability depends on more than electrical continuity. Silicon, copper, underfill, and substrate materials expand differently during temperature changes. TSMC’s 2013 CoWoS reliability work examined underfill and lid choices, including AlSiC versus copper, in relation to interconnect fatigue. That dated study illustrates why the complete assembly must be qualified; it does not prescribe a lid material for every modern package.

What Limits CoWoS-S Interposer Scaling?

CoWoS-S interposer scaling is constrained by stitched routing, defect exposure, wafer utilization, assembly yield, and mechanical control—not by an absolute one-reticle limit.

TSMC has publicly described reticle stitching to extend silicon interposer area beyond a single exposure field. Its 2021 fifth-generation CoWoS-S publication reported an approximately 2,500 mmÂČ interposer supporting multiple logic dies and eight HBM stacks, with five layers of submicron copper wiring and second-generation integrated capacitors. This is a specific published configuration, not a mandatory HBM count or permanent size ceiling.

  • Stitching: interconnects crossing exposure boundaries require controlled pattern alignment and continuity.
  • Yield: increasing area exposes more routing and structures to possible defects; the economics also depend on die and assembly yields.
  • Mechanical integration: larger assemblies require coordinated substrate, underfill, lid, and cooling design.
  • Usable floorplan: logic sizes, HBM placement, power regions, and keep-outs determine how much area is actually available.

Interposer area is not the package outline: the substrate and thermal assembly can extend beyond it. Nor can an area in square millimeters be converted into a package width without knowing the shape.

For larger integration footprints, CoWoS-L uses a wider RDL platform with local silicon interconnects rather than extending one continuous silicon interposer. The TSMC CoWoS overview describes these architecture options; their full comparison belongs in a separate S-versus-L discussion.

Where Is CoWoS-S Packaging Used?

CoWoS-S packaging is used in high-end computing products that need dense connections between processing dies and high-bandwidth memory, including AI acceleration and HPC.

  • AI accelerators: memory bandwidth helps feed compute units with model weights and intermediate data. The benefit depends on the workload, not simply the presence of HBM.
  • HPC processors and accelerators: simulations and other data-intensive calculations can require substantial bandwidth between compute and memory.
  • Multi-die computing designs: a shared interposer provides dense routing between separately fabricated logic and memory components.

TSMC’s 2022 annual report identifies CoWoS-S with high-end HPC and AI and describes HBM3-related qualification. Together with the published eight-HBM fifth-generation example, this provides concrete application context without assuming that every GPU, accelerator, or HBM product uses CoWoS-S. A named chip’s packaging variant still requires its own disclosure.

How Does a CoWoS-S Package Connect to a PCB?

A finished CoWoS-S component connects to the PCB through its package substrate and board-facing terminals, commonly a BGA interface—not through the interposer’s microbumps.

Four distinct levels: dies, interposer, package substrate, and system PCB

The component’s released land pattern, ball map, power requirements, and assembly guidance determine the board design. The PCB routes external interfaces and supplies power; it does not reproduce the fine logic-to-HBM wiring inside the package.

  • Layout: select escape routing and via structures from the actual BGA geometry.
  • Power: design planes, regulator connections, and board decoupling for the component’s current and voltage limits.
  • Assembly: follow the device-specific handling, reflow, warpage, and inspection requirements.
  • Mechanical support: coordinate heatsink attachment, board support, and package keep-outs.

Our guide to advanced HDI PCBs explains board-level routing structures. At EBest Circuit, we support PCB fabrication and PCBA projects around qualified components; we do not claim to manufacture TSMC’s interposers. Send your Gerber files, stackup, BOM, quantities, and package assembly requirements to sales@bestpcbs.com for a board-level review.

FAQs About CoWoS-S

Is CoWoS-S the same as SoIC?

No. CoWoS-S provides interposer-based integration, while SoIC addresses a different level of die stacking and bonding. These technologies can be combined in a larger integration scheme.

Are HBM TSVs and interposer TSVs the same structures?

No. HBM TSVs connect dies within the memory stack; interposer TSVs pass through the separate silicon interposer. They occupy different parts of the package.

Does every CoWoS-S package contain eight HBM stacks?

No. Eight stacks describe one published configuration. The actual count depends on the processor interfaces, memory requirements, floorplan, and qualified package design.

Does reticle stitching mean joining separate pieces of silicon?

No. It joins lithographically patterned regions across exposure fields on the interposer. It does not mean gluing individual silicon tiles together.

Can HBM be replaced like a DIMM?

No. HBM is integrated into the package assembly rather than installed in a board-level memory socket. Replacement is not equivalent to changing a server DIMM.

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Bismaleimide Triazine (BT Resin): Properties, BT Epoxy & FR-4 Comparison

September 18th, 2026

Bismaleimide triazine has become an important resin system for electronic materials that need more dimensional and thermal stability than conventional PCB laminates can provide. It is particularly well known in semiconductor packaging, where thin substrates, fine interconnections, repeated reflow cycles, and moisture sensitivity place tight demands on the laminate.

However, the terminology around BT materials is often inconsistent. BT resin, BT epoxy, BT laminate, BT PCB, and BT substrate do not mean exactly the same thing. Understanding these distinctions is important before comparing material properties or releasing a PCB or substrate specification.

Bismaleimide Triazine BT resin with multilayer PCB laminate and semiconductor package applications

Key Takeaways

  • Bismaleimide triazine, commonly called BT resin, is a high-performance thermosetting resin system used in PCB laminates and semiconductor package substrates.
  • BT is a material family rather than one fixed laminate grade. Tg, Dk, Df, CTE, moisture absorption, and other properties vary with resin formulation, reinforcement, fillers, and cure system.
  • BT epoxy usually refers to a BT resin system modified or blended with epoxy to improve processability, adhesion, toughness, resin flow, or other manufacturing characteristics.
  • BT laminate, BT PCB, and BT substrate are different terms: the first describes the supplied material, while the latter two describe finished electronic structures.
  • Compared with standard FR-4, BT materials are commonly selected where dimensional stability, thermal performance, moisture control, and package warpage are more demanding.
  • BT resin is widely associated with BGA, CSP, SiP, memory, and other organic semiconductor package substrates.
  • BT is not automatically better than FR-4. Standard or high-Tg FR-4 remains more practical for many conventional multilayer PCBs.
  • Engineers should specify an exact material manufacturer and grade instead of requesting only “BT material.”

What Is Bismaleimide Triazine (BT Resin)?

Bismaleimide triazine, or BT resin, is a high-performance thermosetting resin system based primarily on bismaleimide and cyanate-ester chemistry. It is widely used in electronic laminates and organic semiconductor package substrates.

The search phrase bismaleimide triazine BT resin refers to this formulated resin family rather than one universal commercial grade.

During curing, the reactive resin components form a highly crosslinked three-dimensional network. This structure can provide a useful combination of:

  • High glass-transition temperature
  • Dimensional stability
  • Low moisture absorption
  • Thermal resistance
  • Electrical insulation
  • Controlled dielectric properties
  • Good compatibility with multilayer structures

BT resin is not one single chemical compound or one fixed commercial material. Different suppliers can modify the formulation with epoxy, fillers, catalysts, flame retardants, reinforcement, and other additives.

For this reason, an engineer should not assume that every BT laminate has the same Tg, Dk, Df, CTE, or processing conditions.

How Is Bismaleimide Triazine Resin Structured and Cured?

BT resin should be understood as a crosslinked resin system rather than a single molecule with one fixed structure.

A bismaleimide triazine structure is best described as a cured network whose final properties depend on formulation and processing.

Its chemistry generally combines bismaleimide functionality with cyanate-ester chemistry. During curing, cyanate groups can react to form thermally stable triazine-ring structures, while the bismaleimide portion contributes additional crosslinking and heat resistance.

A simplified reaction concept is:

Bismaleimide + Cyanate-Ester Chemistry → Thermal Cure → Crosslinked BT Resin Network

The resulting network can be further modified to balance electrical, mechanical, and processing properties.

Bismaleimide Component

The bismaleimide portion contributes thermal stability and a highly crosslinked structure. Pure BMI systems can be relatively rigid or brittle, so practical electronic formulations are often modified.

Cyanate-Ester Component

Cyanate groups form triazine-ring structures during curing. These structures are associated with high-temperature performance and useful dielectric characteristics.

Modifiers

Commercial BT systems may incorporate epoxy or other modifiers to improve flow, toughness, adhesion, cure behavior, and PCB processing.

Therefore, drawings that show one exact “BT molecule” can be misleading. The material used in an actual laminate is a formulated thermoset system.

What Is the Difference Between BT Resin, BT Epoxy, BT Laminate and BT Substrate?

These terms describe different stages or forms of the material system.

Term Meaning
BT resin Bismaleimide-triazine thermosetting resin chemistry
BT epoxy BT resin system modified or blended with epoxy
BT prepreg Reinforcement impregnated with partially cured BT-based resin
BT laminate Cured reinforced sheet material made with a BT resin system
BT PCB Printed circuit board fabricated using BT-based laminate
BT substrate Finished semiconductor package substrate using BT-based material

The distinction matters during RFQ and material selection. Asking for “BT resin” does not tell a PCB manufacturer which laminate construction, copper foil, glass style, resin content, or cured thickness to use.

Similarly, a BT substrate is not merely a sheet of BT laminate. It is a finished interconnect structure that can contain fine traces, microvias, solder-mask or build-up layers, package pads, and other features.

For more detail on package construction, SAP/mSAP processing, and BT vs ABF, see our BT Substrate: Material, Process and ABF Comparison guide.

BT resin BT epoxy BT laminate and BT substrate terminology comparison

What Properties Matter in a BT Resin Laminate?

The most important BT laminate properties depend on the application. Package substrates may prioritize dimensional stability and moisture behavior, while high-speed boards may place greater emphasis on Dk and Df.

Property Why It Matters
Tg Dimensional and mechanical behavior through thermal cycles
Td Thermal decomposition resistance
X/Y CTE In-plane dimensional stability
Z-axis CTE Via and plated-hole reliability
Dk Impedance, propagation velocity, and trace geometry
Df Dielectric contribution to signal loss
Moisture absorption Package reliability and reflow behavior
Peel strength Copper-to-laminate adhesion
Flexural/mechanical properties Thin-substrate handling and package stability

The values cannot be generalized to every BT material. For example, AGC’s N5000 is a commercially available BT epoxy laminate and prepreg with published dielectric values around Dk 3.6 and Df 0.01 under its specified test conditions.

Those numbers should be treated as one material-grade example, not as a universal BT specification.

Research and commercial formulations can show substantially different Tg and dielectric performance because resin chemistry, fillers, glass reinforcement, resin content, and test method all influence the result.

Always compare exact material grades using the same test method and frequency.

Key BT resin laminate properties including Tg Dk Df CTE moisture and thermal resistance

Why Is BT Resin Used for BGA, CSP and IC Package Substrates?

BT resin is widely used in organic package substrates because semiconductor packaging requires more than ordinary PCB electrical insulation.

A bismaleimide triazine substrate uses this material family to support fine package interconnections and repeated thermal cycles.

A package substrate must maintain dimensional control while dealing with:

  • Fine-pitch package routing
  • Thin core and dielectric structures
  • Multiple lead-free reflow cycles
  • Silicon-to-substrate CTE mismatch
  • Moisture exposure
  • BGA or CSP warpage
  • Fine via and pad registration
  • Package assembly stress

BT-based laminates can provide a useful balance of high-temperature stability, low moisture uptake, mechanical rigidity, and electrical performance.

This is particularly important in thin BGA and CSP structures. Even small dimensional changes can affect solder-ball coplanarity, substrate warpage, trace registration, or package reliability.

BT materials are therefore commonly associated with:

  • BGA substrates
  • CSP substrates
  • Memory packages
  • SiP modules
  • Flip-chip package structures
  • RF and communication modules

The final substrate performance still depends on the exact BT grade, stackup, copper pattern, package size, substrate thickness, and manufacturing process.

Bismaleimide Triazine applications including BGA substrate CSP memory package and RF module

BT Resin vs FR-4: What Is the Difference?

FR-4 and BT resin laminates are both organic electronic materials, but they are normally selected for different performance and cost targets.

Factor FR-4 BT Resin Laminate
Primary use General PCB manufacturing Package substrates and higher-reliability structures
Resin system Primarily epoxy-based BT or BT-epoxy-based
Tg Wide range by grade Often high, but grade-dependent
Dimensional stability Suitable for conventional PCB Better suited to demanding package control
CTE control Depends on grade and reinforcement Low-CTE formulations available
Moisture behavior Grade dependent Often selected for lower moisture sensitivity
Dielectric properties Standard to low-loss grades available Grade dependent; can be optimized for package/high-speed use
Thin-substrate use Possible but not its main strength Common in package substrate applications
Processing familiarity Very mature More material-specific
Material cost Lower Generally higher

The main difference is not simply that BT has a higher Tg. High-Tg FR-4 materials can also provide strong thermal performance.

BT becomes more attractive when several requirements appear together, such as high dimensional stability, low package warpage, moisture resistance, thin substrate construction, repeated reflow reliability, and fine-pitch interconnection.

FR-4 remains the more economical and widely available choice for most conventional PCBs.

Is BT Resin Always Better Than FR-4?

No. BT resin is not automatically a better PCB material than FR-4. It is better suited to certain applications where its material characteristics solve specific reliability or dimensional problems.

Standard or high-Tg FR-4 is usually the practical choice for:

  • Industrial control boards
  • Consumer electronics
  • General multilayer PCBs
  • Power-control boards
  • Cost-sensitive products
  • Conventional SMT assemblies
  • Moderate-density HDI designs

BT becomes more attractive when the product requires:

  • Semiconductor package substrate construction
  • Very thin organic substrates
  • Tighter dimensional stability
  • Lower package warpage
  • Fine-pitch BGA or CSP structures
  • Low moisture sensitivity
  • Higher package-level thermal reliability

Using BT where ordinary FR-4 already meets the electrical and reliability requirements can increase material cost and supply complexity without creating a meaningful product benefit.

The correct decision should come from the complete stackup, package geometry, thermal cycle, electrical requirements, warpage target, and qualification specification.

Where Is Bismaleimide Triazine Used in Electronics?

Bismaleimide triazine materials are most strongly associated with semiconductor packaging, but their use is not limited to one product type.

A bismaleimide triazine PCB may also be specified when a conventional board needs the qualified thermal or dimensional behavior of a BT laminate.

Common applications include:

  • BGA package substrates
  • CSP substrates
  • Memory package substrates
  • System-in-Package modules
  • RF modules
  • Communication modules
  • Selected LED package substrates
  • High-reliability electronic modules
  • Selected high-frequency PCBs
  • Thin multilayer interconnect structures

A BT laminate can also be used for conventional PCB structures when its thermal or dimensional characteristics provide a useful engineering advantage.

However, it should not be assumed that every high-speed PCB needs BT resin. Modern high-speed boards can use multiple material families, including low-loss FR-4 derivatives, PPE/PPO systems, PTFE-based laminates, hydrocarbon ceramics, and other specialty materials.

The application requirement should determine the laminate family, not the material’s reputation alone.

What Are the Manufacturing Challenges of BT Epoxy Laminate?

BT epoxy laminate can require tighter material and process control than a standard FR-4 production flow.

Important manufacturing factors include:

  • Material storage
  • Moisture control
  • Prepreg handling
  • Lamination temperature and pressure
  • Resin-flow control
  • Cure profile
  • Dimensional movement
  • Drilling parameters
  • Desmear conditions
  • Copper adhesion
  • Thin-board handling
  • Warpage control

Moisture Management

Low moisture absorption is an important material characteristic, but storage and handling still matter. Prepreg and thin laminate structures should follow supplier recommendations.

Lamination

BT resin flow and cure behavior differ by formulation. The press cycle should follow the actual laminate supplier’s process window rather than an FR-4 recipe being reused automatically.

Drilling and Hole Preparation

Drill parameters, smear behavior, and desmear chemistry can depend on the cured resin system and glass construction.

Dimensional Stability

Package substrates and thin BT boards may require tighter compensation because small X/Y movement can affect fine-pitch registration.

Warpage

Thin BT-based structures can still warp if copper distribution, build-up symmetry, substrate thickness, package design, or lamination stress is unbalanced. A high-performance resin does not eliminate the need for mechanical stackup control.

BT epoxy laminate manufacturing challenges including lamination moisture drilling desmear and warpage control

How Should Engineers Specify BT Material for PCB Fabrication?

A production drawing should identify the exact BT laminate requirements rather than simply stating “BT material.”

Useful information includes:

  • Material manufacturer
  • Exact material grade
  • Core or prepreg designation
  • Finished dielectric thickness
  • Glass style
  • Resin content
  • Copper foil type and weight
  • Tg and test method
  • Dk and Df test frequency/method
  • X/Y and Z-axis CTE where critical
  • Moisture requirement
  • Finished board thickness
  • Surface finish
  • Controlled impedance
  • Approved alternative materials

For high-frequency designs, Dk and Df values should be tied to the relevant test method and frequency. A Dk value measured by one method should not automatically replace a design Dk obtained through another method.

For thin or packaging-related structures, engineers should also specify dimensional, warpage, and registration requirements where applicable.

“Use BT material” is not enough for a controlled production release. Two BT laminates may differ significantly in processing behavior and electrical performance.

BT laminate specification guide including material grade Tg Td Dk Df glass style copper type and thickness

When Should You Choose BT Resin Instead of Another PCB Material?

Material selection should start from the product requirement rather than choosing BT first and designing around it.

Requirement Material Direction to Consider
General multilayer PCB Standard or high-Tg FR-4
Cost-sensitive electronics FR-4
High-reliability conventional PCB High-Tg / specialty FR-4
BGA/CSP organic package substrate BT resin commonly considered
Thin warpage-sensitive package BT or another qualified package substrate material
Very high-speed PCB Low-loss FR-4, PPE/PPO, PTFE/hydrocarbon or other high-speed materials
Flexible circuit Polyimide
Very high thermal conductivity Ceramic or metal-based structures
Advanced high-density IC build-up BT core, ABF, or other package-specific systems

BT is strongest when thermal, moisture, dimensional, and package-level requirements need to be balanced in one organic material system.

It is not necessarily the first choice for ultra-high-frequency transmission, extreme thermal conductivity, flexible construction, or every advanced IC substrate architecture.

The material decision should therefore consider the entire structure: electrical performance, package geometry, process capability, reliability, cost, supply availability, and customer qualification.

FAQ About Bismaleimide Triazine

1. What does BT stand for in PCB materials?
BT stands for Bismaleimide Triazine, a high-performance thermosetting resin system used in electronic laminates and package substrates.

2. Is BT resin the same as BT epoxy?
No. BT epoxy generally refers to a BT resin system that has been modified or blended with epoxy to adjust processing, adhesion, toughness, or other material properties.

3. Is BT resin better than FR-4?
Not for every PCB. BT is most useful when thermal stability, dimensional control, moisture behavior, package warpage, or semiconductor-substrate requirements justify the additional material cost.

4. Is BT resin used for BGA substrates?
Yes. BT resin is widely associated with BGA, CSP, memory, SiP, and other organic semiconductor package substrates.

5. Does every BT laminate have the same Tg and Dk?
No. BT is a material family. Tg, Dk, Df, CTE, moisture absorption, and other values vary by formulation, reinforcement, resin content, and test method.

6. Is a BT substrate the same as an IC substrate?
A BT substrate is one type of organic IC package substrate. Other IC substrates can use ABF and additional material systems depending on package architecture and interconnect density.

Bismaleimide triazine should therefore be specified as a material system, not as a single fixed-property laminate. Resin formulation, epoxy modification, glass reinforcement, copper construction, thickness, and processing conditions all influence how the finished PCB or substrate performs.

For a PCB project requiring BT laminate or another specialty material, EBest Circuit can review the material grade, stackup, dielectric thickness, copper construction, impedance requirements, finished thickness, and manufacturing constraints before fabrication. Send your project files to sales@bestpcbs.com for DFM review.

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DIP Assembly: Process, SMT vs DIP, Wave Soldering & PCB Guide

September 18th, 2026

DIP assembly remains important even though most modern PCBAs rely heavily on surface-mount technology. Connectors, transformers, relays, terminal blocks, large capacitors, switches, and other mechanically demanding components are still frequently mounted through holes.

The terminology can be confusing because DIP and THT are not technically identical. DIP describes a package format, while THT describes a mounting method. In manufacturing practice, however, many PCBA factories use “DIP assembly” or “DIP line” as shorthand for the entire through-hole insertion and soldering stage.

DIP assembly production area with through-hole component insertion and wave soldering equipment

Key Takeaways

  • DIP assembly is commonly used in PCBA factories to describe the insertion and soldering of through-hole components. Strictly speaking, DIP means Dual In-Line Package, while THT means Through-Hole Technology.
  • A DIP assembly line may handle DIP ICs, connectors, relays, transformers, terminal blocks, electrolytic capacitors, headers, switches, and other leaded components.
  • Modern PCBAs frequently combine SMT and DIP/THT assembly. Small, high-density components are mounted by SMT, while mechanically loaded or larger leaded parts use through-hole mounting.
  • Through-hole components can be soldered by wave soldering, selective soldering, or hand soldering depending on board layout, production volume, component mix, and thermal constraints.
  • PCB design directly affects DIP assembly quality. Finished hole size, annular ring, pad geometry, component spacing, solder accessibility, and bottom-side SMT placement all matter.
  • Common DIP/THT defects include insufficient hole fill, solder bridges, cold joints, icicles, component tilt, incorrect polarity, and flux residue.
  • Inspection and testing may include visual inspection, AOI, ICT, functional testing, programming, and X-ray when hidden structures justify it.

What Is DIP Assembly?

DIP assembly is commonly used in PCB manufacturing to describe the insertion and soldering of through-hole components after or alongside SMT assembly. Strictly, DIP stands for Dual In-Line Package, a package with two parallel rows of leads.

A traditional DIP IC is inserted through plated holes in the PCB and soldered on the opposite side. However, factory DIP lines usually process many other through-hole components that are not technically DIP packages.

Typical factory usage therefore includes:

  • DIP ICs
  • Connectors
  • Relays
  • Transformers
  • Terminal blocks
  • Headers
  • Large electrolytic capacitors
  • Switches
  • Power components

For manufacturing discussions, it is useful to confirm whether “DIP assembly” means only actual DIP-packaged devices or the broader through-hole assembly process.

Is DIP Assembly the Same as Through-Hole Assembly?

Not exactly. DIP is a package style, while THT is a PCB mounting technology.

Term Meaning
DIP Dual In-Line Package
THT Through-Hole Technology
DIP component A component with two parallel rows of leads
THT component Any component whose leads pass through PCB holes
DIP assembly Factory shorthand often used for THT assembly
DIP line Through-hole insertion and soldering production line

A DIP IC is normally a THT component, but many THT components are not DIP packages. A transformer with four leads, a terminal block, or a D-sub connector may all be processed on a DIP line even though none is a standard DIP package.

This distinction matters for engineering documentation. A BOM should specify the actual component package and mounting method rather than relying only on the term “DIP.”

What Components Are Commonly Used in DIP Assembly?

DIP assembly lines handle components that benefit from through-hole mounting or are not available in practical surface-mount formats.

A DIP switch assembly is one example of a through-hole control component that may be inserted and soldered on the same production line.

Common examples include:

  • DIP ICs
  • DIP switches
  • Pin headers
  • Board-to-wire connectors
  • D-sub connectors
  • Terminal blocks
  • Relays
  • Transformers
  • Large electrolytic capacitors
  • Power resistors
  • LEDs
  • Potentiometers
  • Mechanical switches
  • High-force connectors

Through-hole mounting is often selected when the component experiences mechanical loading. Connector insertion and removal, cable forces, relay mass, or transformer weight can make lead-through-hole retention useful.

This does not mean every THT component is automatically more electrically capable or more reliable than an SMT equivalent. The correct choice depends on the component, current, heat, mechanical load, solder-joint design, and operating environment.

Common through-hole components including relay DIP IC electrolytic capacitor transformer connector terminal block pin header and switch

What Equipment Is Used on a DIP Assembly Line?

A DIP assembly line can combine manual workstations, automatic insertion equipment, soldering systems, inspection, and testing.

Typical equipment includes:

  • Lead-forming machines
  • Axial-component insertion machines
  • Radial-component insertion machines
  • Odd-form insertion machines
  • Manual insertion conveyors
  • Component clinching equipment
  • Fluxing and preheating systems
  • Wave soldering machines
  • Selective soldering machines
  • Lead-trimming equipment
  • AOI systems
  • Repair stations
  • ICT fixtures
  • Functional test equipment

The exact configuration depends on volume and component mix. A high-volume appliance board with many repetitive axial parts may justify automatic insertion, while a low-volume industrial assembly with large connectors may rely more heavily on manual insertion.

At EBest Circuit, mixed-technology PCBA projects can be reviewed for SMT, THT insertion, wave soldering, selective soldering, and testing requirements before the production route is finalized.

What Is the DIP Assembly Process?

A typical DIP assembly process starts after component and PCB verification and ends with inspection and electrical testing.

  1. Material and BOM verification. Confirm component part number, polarity, package, lead condition, and quantity.
  2. Lead forming and preparation. Bend, cut, or form leads where required.
  3. Manual or automatic insertion. Insert the component leads through the correct PCB holes.
  4. Pre-solder inspection. Check orientation, polarity, seating, and component location.
  5. Fluxing and preheating. Prepare the solder side for stable wetting.
  6. Wave, selective, or manual soldering. Form the through-hole solder joints.
  7. Lead trimming, touch-up, and cleaning. Remove excessive lead length and repair defects where necessary.
  8. Inspection and testing. Check solder joints and verify electrical function.

The process route can change when the PCB contains both SMT and THT components. Component thermal sensitivity, bottom-side SMT parts, solder pallets, and selective-solder nozzle access all influence the final sequence.

DIP through-hole PCB assembly process from component insertion and pre-solder inspection to wave soldering selective soldering inspection and functional test

SMT vs DIP Assembly: What Is the Difference?

SMT places components directly on PCB surface pads, while DIP/THT assembly passes component leads through drilled holes.

Factor SMT DIP / THT
Mounting On PCB surface Leads through PCB holes
Typical soldering Reflow Wave, selective, or hand soldering
Component density Higher Lower
Hole requirement Usually no component holes Plated through holes required
Automation Highly automated Manual and automatic mix
Typical components BGA, QFN, SMD passives Connectors, relays, transformers, DIP ICs
Mechanical retention Mainly solder-pad attachment Lead passes through board
Board area Usually lower Usually higher

SMT is generally preferred for dense digital electronics because components and pads occupy less area. It also supports high-speed automated placement.

DIP/THT remains useful where component size, mechanical stress, connector retention, legacy parts, or specific power components make through-hole mounting practical.

The two technologies are therefore complementary rather than competing solutions.

SMT versus DIP through-hole PCB assembly comparison with reflow and wave selective soldering

How Are SMT and DIP Combined on the Same PCBA?

Mixed SMT and DIP assembly is common in industrial, automotive-control, power, appliance, medical, and communication electronics.

In production planning, SMT and DIP assembly steps are sequenced to protect components and maintain solder access. An SMT DIP assembly route normally completes reflow before through-hole insertion and wave, selective, or hand soldering.

A typical mixed process can be:

Solder paste printing → SMT placement → reflow → AOI → THT insertion → wave/selective soldering → inspection → functional test

The SMT stage normally installs ICs, resistors, capacitors, QFN/BGA packages, small diodes, and small transistors. The THT stage may then install connectors, relays, transformers, terminal blocks, large capacitors, and mechanical switches.

SMT is often completed first because reflow can process hundreds or thousands of surface joints in one controlled thermal cycle. The through-hole parts are then inserted and soldered using a process compatible with the already assembled board.

The exact sequence is not universal. Bottom-side SMT components, wave-solder pallets, component temperature limits, and board accessibility can require a different manufacturing route.

Wave vs Selective vs Hand Soldering: Which Is Used for DIP Assembly?

The soldering method should be selected from PCB layout, joint count, component density, production volume, and thermal restrictions.

Method Best Fit Main Limitation
Wave soldering Many THT joints, higher-volume boards Large solder-side area exposed to the wave
Selective soldering Mixed SMT/THT and localized joints Slower and more process-specific
Hand soldering Prototypes, rework, odd-form parts Labor and operator dependent

Wave soldering passes the solder side over a controlled wave of molten solder. It is efficient when many through-hole joints can be soldered in one operation.

Selective soldering uses a programmable nozzle or localized soldering system. It is especially useful when only certain THT joints should contact molten solder or when bottom-side SMT parts limit full-wave exposure.

Hand soldering remains useful for prototypes, low-volume builds, rework, unusual connectors, and components that cannot be handled efficiently by wave or selective equipment.

No method is inherently best for every board. The correct process depends on the layout and manufacturing quantity.

Wave soldering selective soldering and hand soldering comparison for DIP through-hole assembly

What PCB Design Rules Matter for DIP Assembly?

DIP/THT assembly quality depends heavily on PCB hole and pad design. A schematic can be correct while the through-hole assembly remains difficult or unreliable because of poor footprint geometry.

Important design items include:

  • Finished hole diameter
  • Component lead diameter
  • Hole-to-lead clearance
  • Annular ring
  • Pad diameter
  • Copper thickness
  • Thermal-relief design
  • Component spacing
  • Wave-solder direction
  • Solder shadowing
  • Selective-solder nozzle access
  • Bottom-side SMT clearance
  • Component height
  • Pin 1 and polarity marking
  • Lead protrusion after soldering

The finished hole must provide enough clearance for insertion and solder flow without becoming excessively large. Too little clearance can make insertion difficult and restrict solder movement, while excessive clearance reduces mechanical support and can complicate hole filling.

Large copper planes can also remove heat from a through-hole pad. Thermal relief may be needed to obtain stable soldering temperature without excessive dwell time.

For selective soldering, nearby components, board edges, fixture features, and nozzle size must also be considered during layout rather than after the PCB is fabricated.

DIP through-hole PCB design showing finished hole annular ring plated hole solder fillet and DIP footprint

What Defects Are Common in DIP Assembly?

Most DIP/THT defects are related to component insertion, solder wetting, hole filling, temperature, or handling.

Common defects include:

  • Insufficient hole fill
  • Cold solder joints
  • Solder bridging
  • Solder icicles
  • Excess solder
  • Solder voids
  • Component tilt
  • Incorrect polarity
  • Wrong component location
  • Missing component
  • Lifted pad
  • Barrel damage
  • Excessive lead protrusion
  • Flux residue

Insufficient hole fill can occur when the solder does not rise adequately through the plated hole. Hole geometry, board thickness, copper planes, flux activity, preheat, solder temperature, and component lead condition can all contribute.

Solder bridging occurs when adjacent joints are unintentionally connected. It can be influenced by pad spacing, lead spacing, solderability, conveyor direction, solder conditions, and component geometry.

Inspection should therefore identify the defect and its process cause rather than treating every poor joint as an operator issue.

DIP through-hole solder joint quality guide showing good joint solder bridge cold joint and insufficient hole fill

How Is DIP Assembly Inspected and Tested?

DIP assembly quality control should verify both component installation and solder-joint performance.

Typical controls include:

  • Incoming component inspection
  • First-article inspection
  • Pre-wave insertion inspection
  • Visual solder-joint inspection
  • AOI where applicable
  • X-ray when hidden geometry justifies it
  • ICT
  • Functional testing
  • Firmware programming
  • Burn-in when specified

Before soldering, inspectors can check component value, orientation, polarity, seating height, missing parts, and lead position.

After soldering, inspection focuses on joint wetting, hole fill, bridges, excess solder, damaged pads, and lead protrusion.

X-ray is not automatically required for every DIP assembly. Most conventional through-hole joints are visible from the solder side, so visual inspection, AOI, ICT, and functional testing are often more useful. X-ray should be applied when hidden geometry or specific reliability requirements justify it.

EBest Circuit supports SPI, AOI, X-ray, ICT, and functional testing according to the actual assembly and inspection needs of the project.

When Should Engineers Choose DIP/THT Instead of SMT?

DIP/THT is most useful when the component or product needs mechanical retention, specific component availability, or a mounting format that SMT cannot provide efficiently.

Typical examples include:

  • Connectors subject to repeated mating forces
  • Terminal blocks with cable loads
  • Heavy transformers
  • Large relays
  • Mechanical switches
  • High-force controls
  • Socketed or serviceable ICs
  • Legacy components
  • Certain large power components

The selection should not be based on a rule that “THT is always stronger” or “SMT is always better.”

Instead, consider mechanical load, component mass, current requirement, thermal environment, available package type, PCB area, assembly volume, automation level, rework requirements, and lifecycle/sourcing.

A mixed approach is often the most practical solution: SMT for density and automation, THT for components that benefit from mechanical through-board attachment.

What Should Buyers Include in a DIP Assembly RFQ?

A DIP assembly quotation should define the bare PCB, through-hole components, assembly process, and acceptance criteria.

Requirement Why It Matters
Gerber / ODB++ PCB fabrication data
BOM Component identification
Pick-and-place / insertion data Component location
Assembly drawing Orientation and polarity
THT component datasheets Lead and package geometry
Solder alloy Process and temperature selection
Wave/selective requirement Production routing
IPC class Acceptance criteria
Test specification ICT/FCT scope
Quantity Manual vs automated process planning

Also specify where applicable:

  • Lead-free or SnPb requirement
  • Conformal coating
  • Programming
  • Burn-in
  • Potting
  • Cleaning requirements
  • Box build
  • Special connector insertion
  • Customer-supplied components

If the soldering method has not yet been selected, the manufacturer can review the PCB layout and component mix before determining whether wave, selective, or manual soldering is most appropriate.

FAQ About DIP Assembly

1. What does DIP stand for in electronics?
DIP stands for Dual In-Line Package, a package with two parallel rows of component leads.

2. Is DIP assembly the same as through-hole assembly?
Not strictly. DIP is a package type, while THT is a mounting technology. However, many PCBA factories use “DIP assembly” as shorthand for their through-hole production stage.

3. What is a DIP assembly line?
A DIP assembly line handles through-hole component preparation, insertion, soldering, inspection, repair, and testing.

4. What is the difference between SMT and DIP assembly?
SMT mounts components directly onto PCB surface pads and typically uses reflow soldering. DIP/THT inserts component leads through drilled holes and normally uses wave, selective, or hand soldering.

5. Can SMT and DIP components be used on the same PCB?
Yes. Mixed SMT and THT assembly is very common, especially on industrial, power, automotive, appliance, and communication boards.

6. Is wave soldering required for every DIP assembly?
No. Selective soldering or hand soldering may be more appropriate depending on the board layout, production quantity, bottom-side SMT components, and component mix.

DIP assembly remains an important part of modern PCBA production because many connectors, relays, transformers, terminal blocks, switches, and other components still benefit from through-hole mounting. The key is to treat DIP/THT requirements as part of the complete PCB and assembly design rather than as a separate manual process added at the end.

For a mixed SMT and DIP assembly project, send your Gerber files, BOM, pick-and-place data, assembly drawings, THT component datasheets, soldering requirements, and test specification to sales@bestpcbs.com for DFM and PCBA review.

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M8 vs M9 CCL: Key Differences for AI Server PCBs

September 18th, 2026

M8 vs M9 CCL is becoming a core material question for AI server PCB design. As 800G networks move toward 1.6T architectures and high-speed SerDes channels move toward 224G-class signaling, M9-class CCL is increasingly discussed as the next step beyond mature M8-class materials.

However, the real engineering question is not whether M9 has a lower nominal Df. The question is whether the complete PCB channel needs enough additional loss margin to justify the higher material cost, tighter supply chain, qualification work, and more demanding multilayer fabrication process.

M8 vs M9 CCL comparison for AI server PCBs showing high-speed multilayer constructions

Key Takeaways

  • M8 and M9 are performance-class descriptions, not universal IPC laminate grades. The exact resin, glass fabric, copper foil, and electrical properties depend on the supplier and material part number.
  • M8-class CCL is already a mature ultra-low-loss option for many 800G switches, AI servers, and high-speed networking boards.
  • M9-class CCL targets even lower transmission loss for next-generation 1.6T networking, longer SerDes channels, and systems with tighter channel-loss budgets.
  • The transition from M8 to M9 is not simply a lower-Df resin upgrade. It usually involves the complete material system: resin, glass fabric, copper profile, lamination behavior, and PCB process control.
  • 224G-class signaling does not automatically require M9. Channel length, via count, connector loss, copper roughness, routing topology, and insertion-loss budget all matter.
  • A 52-layer PCB does not automatically need M9 on every signal layer. Material choice should follow the electrical requirement of each critical channel.
  • M8 remains a practical choice when simulation and validation show sufficient insertion-loss, impedance, and reliability margin.
  • For RFQs, “M9 material” is not enough. Buyers should specify the exact laminate, Dk/Df conditions, copper foil, glass style, stackup, impedance, insertion-loss target, and qualification requirements.

What Do M8 and M9 Mean in CCL Materials?

M8 and M9 are commonly used as performance-class descriptions for high-speed, low-loss CCL systems, rather than as universal IPC material designations.

Two materials described as M9 can therefore have different:

  • Resin chemistries
  • Glass fabrics
  • Copper foil profiles
  • Resin contents
  • Dk and Df values
  • Test methods
  • Processing characteristics

This distinction matters during procurement. A PCB drawing that simply states “M9 material” still leaves too many variables open for accurate stackup design, loss modeling, purchasing, and fabrication.

The correct starting point is the CCL manufacturer and exact material part number, followed by its tested electrical properties, copper construction, glass style, and approved alternatives.

Exploded M8-class and M9-class CCL layer structures with copper foil resin and glass fabric

M8 vs M9 CCL: What Are the Main Differences?

M8-class CCL is already an ultra-low-loss material system for high-speed computing and networking, while M9-class development pushes dielectric loss, conductor loss, dimensional stability, and multilayer process control further for longer and faster channels.

Because M8 and M9 are not universal IPC grades, the most useful comparison combines the general performance direction with published material examples. Panasonic MEGTRON 8 provides a documented M8-class reference, while Doosan DS-7409DYQ illustrates the direction of next-generation material development for 1600G networking and AI accelerators.

Comparison M8-Class CCL M9-Class / Next-Generation CCL
Typical platform target 800G switches, current AI servers, high-speed networking 1.6T switches, next-generation AI accelerators, longer ultra-high-speed channels
Published material example Panasonic MEGTRON 8 R-579Y(U) / R-579Y(N) Doosan DS-7409DYQ
Published application positioning High-speed networking; supports 800GbE Super ultra-low loss for 1600G and AI accelerators
Dk example 3.08 / 3.13 @ 14 GHz 2.50 @ 10 GHz
Df example 0.0012 / 0.0016 @ 14 GHz 0.0006 @ 10 GHz
Tg, DMA 220°C 220°C
Td, 5% weight loss 370°C 380°C
T288 >120 min 120 min
X/Y-axis CTE 17–20 ppm/°C 6 ppm/°C
Z-axis CTE below Tg, α1 50 ppm/°C 25 ppm/°C
Z-axis CTE above Tg, α2 270 ppm/°C 150 ppm/°C
Thermal conductivity Depends on exact construction 0.4–0.5 W/m·K
Water absorption 0.06% 0.06%
Published copper example H-VLP3, 1 oz HVLP3, 1 oz
Published peel strength 0.7 kN/m 0.5 kgf/cm (~0.49 kN/m)
Resin / dielectric direction Mature ultra-low-loss system Further optimized extremely low-loss system
Glass direction Low-Dk / ultra-low-Df glass options Greater emphasis on very-low-loss and dimensionally stable glass construction
Copper requirement Low-profile copper already important Copper roughness becomes more critical as dielectric loss falls
Manufacturing window Relatively mature for experienced high-speed PCB fabs Tighter lamination, registration, copper-interface, thickness, and reliability control
Supply maturity More mature and broadly qualified Fewer qualified material and stackup combinations
Cost direction High Generally higher
Best selection basis Meets channel loss with sufficient engineering margin Consider when M8 no longer provides enough channel-loss or qualification margin

These values show the direction of material development, but they should not be treated as a direct M8-to-M9 percentage comparison. The Panasonic and Doosan data use different frequencies, material constructions, and potentially different measurement conditions. For an actual PCB design, engineers should compare qualified laminate part numbers using the same Dk/Df test method, frequency, glass style, resin content, and copper profile.

M8 vs M9 CCL performance comparison for AI server PCB materials

Why Are AI Server PCBs Moving from M8 Toward M9?

The main reason is that the available channel-loss budget is becoming tighter as data rates increase and signal channels become more difficult.

Several trends are happening at the same time:

  • 112G-class channels are moving toward 224G-class signaling.
  • 800G network architectures are moving toward 1.6T.
  • AI server boards are using more complex multilayer stackups.
  • Long SerDes channels may pass through more vias and connectors.
  • Phase consistency and impedance control are becoming more demanding.

Higher data rate does not automatically mean M9 is mandatory. A short 224G-class channel with limited via transitions and carefully controlled copper roughness may have a very different loss budget from a long midplane or switch-board channel.

The decision therefore depends on the entire transmission path, including routing length, connector loss, via structure, copper profile, stackup, and any retimers in the architecture.

AI server PCB transition from 112G to 224G and 800G to 1.6T with tighter loss budget

How Do M8 and M9 Differ in Dk, Df and Transmission Loss?

Df is usually the first specification engineers compare because it directly influences dielectric loss, but Dk and the test conditions behind both values also matter.

Public material data show the general direction clearly. MEGTRON 8 publishes Dk values around 3.08/3.13 and Df values around 0.0012/0.0016 at 14 GHz, while DS-7409DYQ publishes Dk 2.50 and Df 0.0006 at 10 GHz.

Df mainly affects dielectric loss. As trace length and frequency increase, a lower Df can reduce the amount of signal energy lost in the dielectric.

Dk affects impedance, propagation velocity, and trace geometry. A lower Dk can help some high-speed designs, but the lowest nominal Dk is not automatically the best choice. Stability across frequency, temperature, glass construction, and production lots can be just as important.

For real channel modeling, engineers should use material data measured under conditions that match the qualified stackup as closely as possible rather than comparing datasheet numbers from unrelated test methods.

Why Is M9 a Material-System Upgrade Rather Than Just a Lower-Df Resin?

M9-class development is better understood as a system-level material optimization. Reducing resin Df alone does not guarantee sufficiently low PCB channel loss.

Resin System

The resin must reduce dielectric loss while still supporting multilayer PCB manufacturing. Engineers also need to consider resin flow, thermal reliability, adhesion, dimensional behavior, and CAF resistance.

A resin that looks excellent electrically but creates an unstable lamination process does not solve the complete PCB problem.

Glass Fabric

Glass fabric contributes to effective Dk, Df, dimensional stability, and fiber-weave behavior. Advanced low-loss glass constructions can help reduce dielectric loss and limit local variations that contribute to skew and phase mismatch.

Glass style also affects pressed dielectric thickness and manufacturing behavior, so it should be defined at stackup level rather than treated as an invisible material detail.

Copper Foil

Once dielectric loss is reduced, conductor loss becomes a larger part of the total channel budget. Smoother copper becomes increasingly valuable because surface roughness increases conductor loss at high frequency.

This is why many M9-class designs place greater emphasis on very-low-profile copper in addition to lower-loss resin and glass. Our existing HVLP Copper Foil for AI Server PCBs guide explains this conductor-loss mechanism in more detail.

M9 material system upgrade showing low-loss resin advanced glass fabric smooth copper foil and multilayer PCB

How Much Does Copper Roughness Matter in M8 and M9 PCBs?

Copper roughness can determine how much of the theoretical low-loss advantage of a laminate remains after PCB fabrication.

At high frequency, current concentrates near the conductor surface because of the skin effect. If that surface is rough, the effective current path becomes more complex, increasing conductor loss.

This means a lower-Df resin can still deliver disappointing channel performance if the signal layer uses an unsuitable copper surface.

For M8 and M9 projects, engineers should evaluate:

  • Copper foil type
  • Roughness data such as Rz or Rq
  • Treatment side
  • Foil thickness
  • Inner-layer surface treatment
  • Final insertion-loss performance

The incoming copper foil grade is only one part of the story. PCB processing can also change the effective copper-dielectric interface, so overly aggressive inner-layer treatment can reduce the benefit of starting with smoother foil.

M9 does not automatically mean HVLP5. Published next-generation low-loss material data can still include HVLP3 copper constructions, which is why the M9 label alone should never be translated into a mandatory copper grade.

Smooth copper versus rough copper showing lower and higher conductor loss in high-speed PCB traces

When Is M8 CCL Still Enough for an AI Server PCB?

M8 remains a strong choice when the complete channel meets the required electrical targets with sufficient engineering margin.

Typical situations include:

  • High-speed channels are relatively short.
  • Via transitions are limited.
  • Connector loss is manageable.
  • Simulation shows acceptable insertion loss.
  • Existing M8 materials are already customer-qualified.
  • Production experience with the stackup is mature.
  • Supply availability and lead time are important.
  • Only some signal layers carry the most demanding SerDes channels.

An M8 stackup may therefore remain entirely appropriate even in an advanced AI server platform.

If an M8-based design already meets insertion-loss, impedance, and reliability requirements with sufficient margin, moving to M9 may increase cost without producing a measurable system-level benefit.

This is especially important for boards where only a small portion of the routing approaches the channel-loss limit.

When Should Engineers Consider M9 CCL?

M9 becomes more relevant when the M8 design begins to consume too much of the available channel-loss margin.

Typical triggers include:

  • Long 224G-class SerDes channels
  • 1.6T switching architectures
  • High-loss midplane or backplane routes
  • Multiple via transitions
  • Very dense high-speed routing
  • M8 simulation results close to the insertion-loss limit
  • Customer-specified or platform-qualified M9 materials
  • Architectures trying to preserve margin without adding additional retimers

The decision should still be based on the actual channel model. A short trace on a high-layer-count PCB may have less need for M9 than a long route on a lower-layer board.

The trigger for M9 should be the channel-loss budget and platform-qualification requirement, not the PCB layer count alone.

Does a 52-Layer or Higher-Layer PCB Automatically Require M9?

No. A 52-layer or higher-layer PCB does not automatically require M9 material on every layer.

A high-layer-count AI server PCB may contain:

  • Critical high-speed SerDes signal layers
  • Lower-speed control signals
  • Clock or management interfaces
  • Power planes
  • Ground planes
  • Auxiliary signal layers

Only some of these layers may be sensitive enough to justify the most aggressive low-loss construction.

In some designs, engineers may consider a hybrid material strategy in which the most demanding signal regions use a higher-performance material system while other layers follow a different qualified construction. Whether this is practical depends on lamination compatibility, reliability, stackup design, and the fabricator’s process capability.

Layer count therefore tells you how difficult the board may be to manufacture, but it does not by itself define the required loss class.

What PCB Manufacturing Challenges Increase with M9-Class CCL?

M9-class materials can narrow the PCB manufacturing window because the electrical advantage must be maintained through lamination, drilling, plating, and inner-layer processing.

Important manufacturing challenges include:

  • Multilayer lamination control
  • Resin-flow consistency
  • Pressed dielectric thickness
  • Layer-to-layer registration
  • Copper adhesion
  • Inner-layer surface treatment
  • Mechanical drilling quality
  • Plated-through-hole reliability
  • Controlled impedance
  • Insertion-loss verification
  • Material-lot control

Extremely smooth copper needs enough adhesion without introducing excessive surface roughness during inner-layer treatment. This creates a direct trade-off between electrical performance and process robustness.

Advanced glass constructions can also change drilling behavior. Where a qualified M9 construction uses harder low-loss glass, tool wear, hole-wall quality, and drilling parameters may require tighter control.

Before quoting an M9 PCB, the fabricator should review the exact laminate system, stackup, copper foil, glass style, finished thickness, via structure, impedance requirements, and customer qualification rules.

How Should Engineers Choose Between M8 and M9 for a Real PCB Stackup?

The most reliable selection method is to start with the channel requirement and work backward to the material system.

  1. Define the signaling rate and channel topology. Identify connectors, vias, trace lengths, and any retimers.
  2. Build the insertion-loss budget. Determine how much loss the PCB portion of the channel can consume.
  3. Identify the longest and most critical channels. Do not optimize every route based on the worst case unless necessary.
  4. Simulate an M8 stackup using realistic copper roughness. Nominal Df alone is not enough.
  5. Compare the remaining margin with an M9 alternative. Evaluate whether the improvement is electrically meaningful.
  6. Confirm the stackup with the PCB fabricator. Check actual cores, prepregs, glass styles, copper foils, thickness tolerances, and material availability.

The fabricator should be involved before the stackup is frozen. A theoretically ideal dielectric thickness or glass style may not be the construction the factory can source and process consistently.

This step becomes more important as layer count increases because small dielectric-thickness and registration changes can affect impedance, board thickness, and production yield across many lamination interfaces.

What Should Buyers Include in an M8 or M9 PCB RFQ?

An RFQ should define the material system and electrical target clearly enough that the PCB manufacturer does not have to guess what “M8” or “M9” means.

RFQ Item Why It Matters
CCL manufacturer and exact part number Avoids ambiguous M8/M9 descriptions
Approved alternative materials Supports supply continuity
Dk/Df and test frequency/method Makes electrical data comparable
Copper foil type and roughness Controls conductor-loss assumptions
Glass style Affects loss, skew, thickness, and processing
Resin content Influences pressed dielectric behavior
Layer count Defines stackup complexity
Finished board thickness Sets lamination target
Impedance table Defines trace geometry requirements
Insertion-loss target Establishes electrical acceptance criteria
Coupon / S-parameter requirement Defines production verification
Customer-approved material list Controls qualification compliance

For a high-speed AI server project, the RFQ should also state the via structure and identify the most critical high-speed layers whenever possible.

Writing only “M9 material, 52 layers” is not enough for a reliable technical quotation because two suppliers may interpret that requirement using very different laminate, copper, and glass constructions.

M8 and M9 PCB RFQ checklist including exact material Dk Df copper foil glass style stackup impedance and insertion loss

FAQ About M8 and M9 CCL

1. Is M9 CCL always better than M8 CCL?
No. M9 CCL generally targets lower transmission loss, while M8 CCL remains suitable when it meets the channel budget with sufficient margin.

2. Can M8 CCL support 224G-class signals?
Potentially, yes. The result depends on trace length, copper roughness, via count, connectors, routing topology, and the complete insertion-loss budget rather than the M8 label alone.

3. Does every M9 CCL use Q-glass?
No. The search phrase M9 CCL Q glass describes one material direction, but the exact glass fabric must be checked in the qualified laminate construction.

4. Does M9 CCL require HVLP5 copper foil?
No. The required copper profile depends on the qualified material system, channel-loss target, signal layer, and customer approval.

5. Does a 52-layer PCB need M9 on every layer?
No. Material selection should follow the electrical role of each layer and the loss requirements of the critical channels rather than total layer count alone.

6. What information is needed to quote an M9 PCB?
Provide the exact laminate, approved alternatives, stackup, copper foil, glass style, finished thickness, impedance requirements, insertion-loss target, via structure, quantity, and qualification requirements.

Selecting between M8 and M9 requires more than comparing nominal Dk and Df values. Channel length, copper profile, glass construction, stackup, via structure, manufacturing capability, and customer qualification requirements should be evaluated as one system.

For an AI server or high-speed network PCB review, send your Gerber files, stackup, target material, impedance table, insertion-loss requirements, finished board thickness, via structure, and expected quantity to sales@bestpcbs.com.

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PCB Cards: Types, Card Edge Design, Assembly & Manufacturing Guide

September 18th, 2026

The term PCB cards appears frequently in electronics, but it does not describe one standardized type of printed circuit board. An engineer may use the term for a plug-in communication card, a bare circuit card, an assembled controller board, or even an NFC business card.

For PCB manufacturers, that ambiguity matters. Before fabrication or assembly begins, the actual card function, mechanical interface, component state, stackup, connector requirements, and testing scope must be defined. This guide explains the common meanings of PCB cards and the design and manufacturing details that make card-type PCBs different.

PCB cards including a card-edge board, assembled controller card, NFC PCB card, and diagnostic test card

Key Takeaways

  • A PCB card is an informal term for a printed circuit board used as an electronic card or module. Depending on context, it may mean a bare PCB, an assembled circuit card, or a plug-in board.
  • PCB cards include controller cards, PCIe-style cards, communication cards, card-edge modules, diagnostic cards, NFC cards, and PCB business cards.
  • PCB card, circuit card, PCBA, and circuit card assembly are related terms but should not automatically be treated as identical.
  • Plug-in PCB cards often use gold fingers along the board edge to mate directly with a socket or card-edge connector.
  • Gold-finger design depends on connector pitch, PCB thickness, plating, bevel, mechanical tolerance, insertion cycles, and the manufacturer’s fabrication process.
  • A PCB being called a “card” does not define its laminate. Standard FR-4, high-Tg FR-4, and low-loss materials can all be used depending on the application.
  • Manufacturing files should clearly specify the board outline, connector interface, gold fingers, stackup, impedance, assembly data, and testing requirements.

What Is a PCB Card?

A PCB card is a printed circuit board used as a functional electronic card or module. Depending on the industry and project documentation, it can refer to either a bare printed circuit board or a populated assembly.

The word “card” is especially common when the board is designed to:

  • Plug into another PCB or backplane
  • Fit into a defined slot or chassis
  • Act as a replaceable functional module
  • Use edge contacts as an electrical interface
  • Carry a specific control, communication, storage, or test function

Typical examples include network interface cards, industrial I/O cards, motor-control cards, PCIe expansion cards, communication modules, and diagnostic cards.

The important point is that “PCB card” does not automatically tell a manufacturer whether components are assembled. That information must come from the BOM, assembly drawing, pick-and-place data, and purchasing specification.

What Are the Main Types of PCB Cards?

PCB cards can be grouped by their mechanical interface, assembly state, and intended function.

PCB Card Type Typical Example Main Characteristic
Bare circuit card Unassembled controller PCB PCB fabrication only
Assembled circuit card Industrial control module Components already mounted
Plug-in PCB card PCIe or communication card Inserts into a socket or backplane
Card-edge PCB Memory or interface module PCB edge acts as connector
Test card Diagnostic or interface board Used for test and verification
NFC PCB card Smart identification card PCB antenna and NFC IC
PCB business card Promotional electronic card PCB used as functional branding item

The same card can fit more than one category. For example, a communication board can be both an assembled circuit card and a card-edge PCB.

For manufacturing, the functional label is less important than the actual requirements: stackup, board dimensions, copper thickness, connector geometry, surface finish, components, and test criteria.

Main types of PCB cards including bare circuit card assembled card card-edge module test card and NFC PCB card

PCB Card vs PCB vs PCBA vs Circuit Card Assembly

These terms overlap, but they describe different things in manufacturing documentation.

Term Most Common Meaning
PCB Printed circuit board; may refer to a bare board or the general technology
PCB card Informal term for a board used as an electronic card/module
Circuit card Often another name for a PCB or functional electronic card
PCBA Printed circuit board assembly with components installed
CCA Circuit card assembly; populated functional card
Plug-in card PCB module designed to insert into another system
Card-edge PCB PCB with plated edge contacts that mate directly with a connector

A bare PCB card has copper circuitry, holes, pads, solder mask, and surface finish but no electronic components. Once components are assembled, it becomes a PCBA or circuit card assembly.

In procurement documents, engineers should therefore avoid relying only on the words “PCB card” or “circuit card.” Specify whether the requirement covers bare-board fabrication, component assembly, programming, functional testing, or a complete tested module.

For a broader terminology comparison, see our guide to Circuit Card vs Circuit Board.

PCB card versus PCB versus PCBA versus CCA terminology comparison

How Does a Plug-In PCB Card Work?

A plug-in PCB card is designed as a removable electronic module that connects electrically and mechanically to another board, backplane, or system socket.

A typical connection path is:

PCB card → edge contacts or connector → motherboard/backplane → system power and signals

The card may carry:

  • Processor or FPGA circuitry
  • Network interface
  • Storage interface
  • Industrial I/O
  • Motor control
  • Power conversion
  • Data acquisition
  • Test electronics

Unlike a permanently wired PCB, a plug-in card must also satisfy mechanical requirements such as insertion alignment, connector retention, board thickness, chassis position, and repeated mating.

High-speed cards add another layer of complexity because the connector interface becomes part of the signal channel. Differential-pair geometry, breakout routing, via stubs, reference-plane continuity, and connector insertion loss may all affect performance.

This is why plug-in PCB cards should be treated as both an electrical design and a mechanical interface.

Plug-in PCB card showing gold fingers mating with a card-edge connector for power and signals

What Is a PCB Card-Edge Connector?

A PCB card-edge connector uses plated contacts along the edge of the PCB itself as one half of the connector interface.

The PCB slides into a matching socket, and spring contacts inside the connector press against the plated pads—commonly called gold fingers.

A card-edge interface may include:

  • Single-sided or double-sided contacts
  • Different contact pitches
  • Power and signal contacts
  • Ground contacts
  • Staggered contact lengths
  • Keying slots
  • Beveled insertion edges
  • Controlled PCB thickness

This construction removes the need for a separate board-mounted connector on the card itself, which can save space and reduce component count.

However, the PCB edge becomes a precision mechanical feature. Board thickness, routing profile, bevel, plating, pad position, and connector tolerance all need to match the mating connector drawing.

For high-speed interfaces, the card edge also becomes part of the controlled-impedance signal path.

What Design Rules Matter for PCB Card Gold Fingers?

Gold fingers must provide low contact resistance, corrosion resistance, and sufficient wear resistance for the expected mating cycles.

The main design items include:

  • Contact pitch
  • Finger width and length
  • PCB thickness
  • Nickel and gold plating requirements
  • Solder-mask clearance
  • Copper-to-edge spacing
  • Bevel angle and depth
  • Keying position
  • Connector insertion depth
  • Required mating-cycle life

Hard gold is commonly preferred for repeated-mating card-edge contacts because it offers better wear resistance than standard solderable surface finishes. The exact gold thickness should follow the connector life, customer specification, and fabrication capability rather than a universal value.

The leading edge may also require a bevel to reduce insertion force and prevent the connector contacts from being damaged. Bevel geometry is determined by the card thickness and mating connector; common designs may use an angled edge in roughly the 30°–45° range, but the connector drawing should control the final specification.

Gold fingers should also be kept free of solder mask, silkscreen, solder paste, surface contamination, and routing damage. For high-current card contacts, power fingers may need wider copper geometry than ordinary signal contacts.

PCB card gold finger design showing hard gold pitch bevel edge and board thickness

What PCB Materials and Stackups Are Used for Card-Type Boards?

“PCB card” describes the board’s role, not its laminate type. The correct material depends on electrical performance, mechanical strength, thermal environment, and product qualification requirements.

Application Common Material Direction
General controller card Standard FR-4
Industrial card High-Tg FR-4
High-speed communication card Low-loss / high-speed laminate
High-current power card Heavier copper or thicker copper planes
Flexible interface card FPC
Compact 3D module Rigid-flex PCB

A simple industrial I/O card may use a conventional multilayer FR-4 construction, while a PCIe or high-speed networking card may require lower Dk/Df materials, controlled impedance, tighter dielectric tolerances, and insertion-loss verification.

Mechanical requirements also matter. Card-edge connectors are often designed for a specific finished board thickness, so the PCB stackup must meet both electrical and connector-fit requirements.

For high-speed cards, stackup decisions should also consider differential impedance, reference-plane continuity, trace-to-plane spacing, copper roughness, glass weave, via structure, and insertion-loss budget.

The material should therefore be selected from the interface and channel requirements rather than from the word “card.”

What Are PCB Test Cards Used For?

A PCB test card is a board designed to support electrical testing, diagnostics, qualification, or connection between a device under test and test equipment.

Depending on the project, the term may describe:

  • Diagnostic card
  • Interface card
  • Fixture interface PCB
  • Production test board
  • Burn-in card
  • Signal breakout card
  • Calibration board

For example, a test card can connect production equipment to a DUT through pogo pins, edge connectors, sockets, or cable interfaces.

Some test cards carry active circuits for signal conditioning or measurement, while others mainly route signals between test equipment and the product.

Because PCB test card is not one standardized construction, an RFQ should define the actual application. Useful information includes DUT interface, test voltage/current, signal frequency, connector type, insertion cycle requirements, expected test volume, controlled-impedance requirements, and functional test procedure.

This prevents a manufacturing supplier from treating a demanding high-cycle test card like an ordinary low-volume PCB.

What Are NFC PCB Cards and PCB Business Cards?

NFC PCB cards are thin printed circuit boards that integrate an NFC antenna, NFC IC, and sometimes LEDs, sensors, QR codes, or other electronics.

Most NFC systems operate at 13.56 MHz. A typical NFC PCB card may include:

  • PCB loop antenna
  • NFC IC
  • Matching or tuning components
  • Memory
  • LED indicator
  • QR code or printed information

PCB business cards often use dimensions close to the ISO ID-1 credit-card format, approximately 85.60 × 53.98 mm, although custom sizes are also common.

A PCB business card does not have to include NFC. It may instead use a QR code, LED circuit, USB interface, small development circuit, measurement reference, functional tool, or decorative copper artwork.

For an NFC version, antenna geometry is critical. Trace width, spacing, number of turns, board thickness, copper environment, nearby ground planes, and metal objects can change antenna inductance and resonance.

The electrical tuning should therefore be verified on the final PCB construction rather than assumed from the CAD geometry alone.

NFC PCB card and PCB business card showing antenna coil NFC IC and 13.56 MHz operation

How Are PCB Cards Manufactured and Assembled?

PCB card manufacturing follows the standard PCB production flow, with additional attention to edge geometry and connector interfaces where required.

A typical process is:

Gerber / ODB++ review → PCB fabrication → profile routing → surface finish → gold-finger processing → electrical test → SMT → THT → inspection → functional test

For a card-edge PCB, fabrication may require extra controls for:

  • Gold-finger plating
  • Edge bevel
  • Connector key slots
  • Board thickness
  • Finger position
  • Profile tolerance
  • Contact-edge quality

During PCBA, the production flow can include solder paste printing, SPI, SMT placement, reflow soldering, AOI, THT insertion, wave or selective soldering, X-ray where required, programming, and functional testing.

The card connector area should be protected during assembly so that solder, flux, scratches, or handling contamination do not degrade the contact surface. Dimensional inspection is also more important than on a PCB that never mates with a precision slot.

PCB card manufacturing and testing flow from Gerber design to fabrication gold fingers SMT AOI and functional test

How Should PCB Cards Be Inspected and Tested?

The test plan should match the PCB card’s function rather than automatically applying every available inspection method.

For bare PCB cards, common checks include:

  • Electrical continuity/isolation test
  • Board dimensions
  • Finished thickness
  • Hole and slot dimensions
  • Gold-finger geometry
  • Surface finish
  • Controlled impedance where required

For assembled cards, additional inspection can include SPI, AOI, X-ray, ICT, flying-probe test, functional test, and firmware programming.

Card-edge modules may also require contact continuity, connector fit, insertion/removal inspection, finger plating verification, and mechanical gauge checks.

High-speed cards may require TDR, impedance coupon testing, insertion loss, S-parameters, eye-diagram testing, or system-level validation. Not every PCB card needs these tests; the acceptance plan should follow the interface, signal rate, reliability target, and customer specification.

What Files Are Needed to Quote a Custom PCB Card?

A complete RFQ should define both the PCB and the card interface.

File / Requirement Purpose
Gerber or ODB++ Defines PCB fabrication data
Stackup Defines layer and dielectric structure
Board outline Controls card dimensions
Mechanical drawing Defines slots, cutouts and tolerances
Connector drawing Confirms mating interface
Gold-finger specification Defines plating and bevel requirements
BOM Defines assembly components
Pick-and-place file Provides SMT coordinates
Assembly drawing Confirms component orientation
Impedance table Defines controlled-impedance requirements
Test specification Defines acceptance and functional testing
Quantity Supports material and process planning

If a card-edge connector is used, also specify finished PCB thickness, finger pitch, hard-gold requirement, bevel requirement, insertion-cycle requirement, and keying dimensions.

For high-speed PCB cards, include the target stackup, differential impedances, critical interfaces, and any insertion-loss requirement.

The more clearly the interface is defined, the less risk there is that a board can pass electrical fabrication checks but fail to fit or function correctly in the final system.

FAQ About PCB Cards

1. What is a PCB card?
The search query what is PCB card usually refers to a printed circuit board used as a functional electronic card or module. It may be bare, assembled, or designed as a plug-in module.

2. Is a PCB card the same as a circuit card?
Often, but not always. Both terms can describe a printed circuit board, while the exact meaning depends on the industry and project documentation.

3. Is a PCB card the same as a PCBA?
Not necessarily. A PCBA specifically contains assembled components, while “PCB card” can also refer to a bare card-type PCB.

4. Why do PCB cards use gold fingers?
Gold fingers provide durable, corrosion-resistant electrical contacts between the PCB card and a card-edge connector.

5. Can a PCB card include NFC?
Yes. An NFC PCB card can integrate a 13.56 MHz antenna and NFC IC, along with memory, LEDs, or other functions.

6. What should I send a PCB manufacturer for a custom card quote?
Provide Gerber or ODB++, stackup, mechanical drawing, connector and gold-finger specifications, BOM, pick-and-place data, assembly drawing, impedance requirements, test requirements, and order quantity.

PCB cards range from simple controller boards to high-speed plug-in modules, so the word “card” alone is not enough to define a manufacturing requirement. Mechanical interface, assembly scope, connector geometry, stackup, surface finish, and test criteria should be specified together.

For a custom PCB card or circuit card assembly project, send your Gerber files, stackup, mechanical drawings, BOM, pick-and-place files, gold-finger requirements, and test specifications to sales@bestpcbs.com for DFM and manufacturing review.

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PCB Bow & Twist: IPC Limits, Measurement & Calculation Guide

September 18th, 2026

PCB bow and twist are forms of PCB warpage that can affect solder paste printing, component coplanarity, connector fit, automated handling, and final mechanical assembly. The percentage may look small, but on a large or thin PCB, even a fraction of one percent can produce several millimeters of displacement.

For engineers and buyers, the practical questions are therefore not only “Is the board warped?” but how the deformation is classified, how it is measured, which IPC requirement applies, and whether the board meets the agreed flatness specification.

PCB Bow and Twist measurement on a precision surface plate

Key Takeaways

  • PCB bow is a curved deformation, while PCB twist is a diagonal deformation that lifts one corner out of the plane formed by the other three corners.
  • IPC-6012F specifies a default maximum bow and twist of 0.75% for printed boards using surface-mount components and 1.5% for other printed boards, unless procurement documentation specifies otherwise.
  • IPC-TM-650 2.4.22 is the key test method for determining bow and twist percentage on rigid printed boards, rigid portions of rigid-flex boards, and multiple-board panels.
  • For bow, the measured gap is divided by the corresponding board length or width. For production-method twist, the lifted-corner gap is divided by twice the board diagonal.
  • A 200 × 300 mm SMT PCB with a 0.75% limit allows 1.50 mm bow across the 200 mm direction, 2.25 mm across the 300 mm direction, and approximately 5.41 mm raised-corner gap for the IPC production twist method.
  • Asymmetric stackups, uneven copper distribution, material construction, lamination conditions, and later thermal or mechanical stress can all contribute to PCB warpage.
  • The IPC 0.75% value is an acceptance limit, not necessarily the optimum flatness target for every assembly.

What Are PCB Bow and Twist?

PCB bow and twist are two different forms of deviation from flatness. PCB bow is roughly cylindrical or spherical curvature in which the four corners of a rectangular board remain in one plane, while twist occurs along a diagonal so that one corner lies outside the plane formed by the other three.

Characteristic PCB Bow PCB Twist
Typical shape Arc, hump, or shallow dome Propeller-like diagonal distortion
Corner condition Four corners can remain coplanar One corner lifts relative to the other three
Main measurement reference Board length and width Board diagonal
Production measurement Maximum gap along an edge direction Raised-corner gap

A board can also show a combination of bow and twist. In that case, simply measuring the highest point from a tabletop does not necessarily produce the correct IPC percentage.

The test setup and calculation method need to match the type of deformation being evaluated.

PCB bow compared with PCB twist deformation

What Is the IPC Standard for PCB Bow and Twist?

IPC-6012F specifies that, unless otherwise stated in the procurement documentation, finished rigid printed boards designed in accordance with IPC-2221 have a maximum bow and twist of 0.75% when surface-mount components are used and 1.5% for other printed boards.

Board Application Default IPC-6012F Maximum
Printed board using surface-mount components 0.75%
Other printed boards 1.50%

These percentages are default acceptance requirements, not universal design targets. A customer drawing, procurement specification, or product-specific requirement can call for tighter flatness.

Finished boards are also assessed in their delivered form. If boards are supplied in pallet arrays for assembly, the bow and twist requirement for the array may be agreed separately between the user and supplier.

IPC-TM-650 2.4.22 vs 2.4.22.1: What Is the Difference?

IPC-TM-650 2.4.22 and 2.4.22.1 sound nearly identical, but they report flatness differently.

Test Method Main Purpose Result
IPC-TM-650 2.4.22C Bow and twist of rigid boards, rigid portions of rigid-flex, and multiple-board panels Percentage
IPC-TM-650 2.4.22.1C Maximum vertical displacement of panels, finished rigid boards, and rigid portions of rigid-flex Displacement in mm/in

Method 2.4.22 includes production Go/No-Go procedures for bow and twist, plus a more precise referee procedure for twist. It uses a precision surface plate, feeler or pin gauges, measuring devices, and, for the referee method, additional support and dial-indicator equipment.

Method 2.4.22.1 instead records the maximum vertical displacement of an unrestrained specimen. Its scope applies to laminates at least 0.5 mm [0.020 in] thick and can also be used after etching or thermal stress when agreed between user and supplier.

These methods should therefore not be treated as interchangeable calculations.

How Do You Measure PCB Bow?

PCB bow is measured by placing the board on a precision flat surface with the convex side facing upward and measuring the gap created by the curvature. A bow and twist PCB check should classify the deformation before selecting the measurement method.

For the IPC-TM-650 2.4.22 production method:

  1. Measure the board length L and width W.
  2. Place the board on a precision surface plate, convex side upward.
  3. For the edge being checked, apply enough pressure at both corners of that edge to bring them into contact with the datum surface.
  4. Insert a feeler or pin gauge between the PCB and surface plate.
  5. Determine the largest gauge that fits for the length and width directions.
  6. Record these measurements as RL and RW.
  7. Calculate bow percentage separately for length and width.

IPC calculates bow in the corresponding board direction. The denominator is not automatically the PCB diagonal.

This distinction matters because using the diagonal would produce a lower calculated percentage and could incorrectly classify an out-of-tolerance board as acceptable.

PCB bow measurement using a precision surface plate and feeler gauge with length width and gap dimensions

How Do You Measure PCB Twist?

For production testing, PCB twist is measured by placing three corners of the board against a flat datum surface and measuring the gap beneath the remaining lifted corner.

The IPC-TM-650 2.4.22 procedure is:

  1. Measure the board diagonal and record it as D.
  2. Place the PCB on the surface plate.
  3. Position it so that three corners contact the surface.
  4. If necessary, restrain only one corner to establish three-point contact.
  5. Insert a feeler or pin gauge under the remaining lifted corner.
  6. Find the largest gauge that fits without lifting the other three corners.
  7. Record that gap as R.
  8. Calculate the twist percentage.

The production formula contains a factor of two because constraining one corner against the surface plate approximately doubles the observed vertical twist deflection.

If three corners cannot be brought into contact by restraining only one corner, the referee method should be used instead of forcing the production procedure.

PCB twist measurement showing board diagonal D and raised corner gap R on a precision surface plate

What Is the PCB Bow and Twist Formula?

IPC-TM-650 2.4.22 uses different formulas for bow and production-method twist. A PCB bow and twist calculator must use the correct board direction or diagonal for the deformation being measured.

Bow in the length direction:

BowL (%) = (RL / L) × 100

Bow in the width direction:

BowW (%) = (RW / W) × 100

Where:

  • RL = maximum measured gap in the length direction
  • RW = maximum measured gap in the width direction
  • L = PCB length
  • W = PCB width

Twist — production method:

Twist (%) = (R / (2 × D)) × 100

Where:

  • R = maximum gap under the raised corner
  • D = PCB diagonal

The factor of two should not be removed when using this IPC production measurement method.

For a rectangular PCB, the diagonal is:

D = √(LÂČ + WÂČ)

How Do You Calculate PCB Bow and Twist?

Consider a 200 × 300 mm PCB that will use SMT components. Using the default IPC-6012F limit of 0.75%, the maximum allowable production-measurement gaps can be calculated before inspection.

The PCB bow and twist percentage must always be evaluated against the board dimensions and the agreed acceptance limit.

PCB dimensions

  • Width = 200 mm
  • Length = 300 mm
  • Bow/twist limit = 0.75%

First calculate the board diagonal:

D = √(200ÂČ + 300ÂČ) = 360.56 mm

The allowable gaps are:

Calculation Formula Maximum Gap
Bow across 200 mm direction 200 × 0.75% 1.50 mm
Bow across 300 mm direction 300 × 0.75% 2.25 mm
Twist production gap 2 × 360.56 × 0.75% 5.41 mm

Now assume the measured 300 mm-direction bow gap is 1.80 mm:

Bow = (1.80 / 300) × 100 = 0.60%

That result is below 0.75%.

If the measured lifted-corner gap for twist is 4.00 mm:

Twist = (4.00 / (2 × 360.56)) × 100 ≈ 0.55%

That result is also below 0.75%.

This example shows why a physical gap in millimeters cannot be judged by itself. The same displacement produces a different bow or twist percentage depending on board dimensions.

What Causes PCB Bow and Twist?

PCB bow and twist usually result from uneven internal stress rather than one isolated defect. The source can enter during design, material preparation, fabrication, or later thermal processing.

Evaluating bow and twist in PCB production starts with identifying where uneven stress entered the process.

PCB Design

Common design-related contributors include asymmetric stackups, unequal copper weights above and below the centerline, large differences in local copper density, large cutouts, and panel breakaway areas that do not reflect the copper distribution of the finished board.

Materials

Glass-fabric orientation, core and prepreg construction, CTE mismatch, mixed laminate systems, and moisture condition can affect dimensional stability.

PCB Manufacturing

Press conditions, incomplete cure, incorrect prepreg construction, uneven heating or cooling, solder-mask cure, and hot-air solder leveling can introduce or release stress.

Assembly and Handling

Mechanical loading, storage, reflow, fixtures, conveyor support, and asymmetric component mass can further change the board shape.

A useful way to think about these mechanisms is that some stress is built into the PCB during lamination, while other deformation is introduced later by handling or thermal processing.

Why Does Copper Distribution Affect PCB Warpage?

Copper and dielectric materials respond differently to temperature and processing stress, so an unbalanced copper pattern can create unequal forces through the PCB thickness.

The problem can occur in two ways:

  • Layer-to-layer imbalance: one side of the stack has heavier copper or larger plane areas than its mirrored layer.
  • Local imbalance: one region contains dense copper while another region contains very little copper.

During multilayer pressing, copper density also affects resin flow and local pressure. During later thermal cycles, different copper distributions can contribute to unequal expansion and stress.

A symmetrical stackup with similar copper weights and coverage on corresponding layers reduces this risk. Panel breakaway areas should also avoid extreme copper-density differences compared with the PCB itself.

Copper filling or thieving may help balance sparse areas, but it should still respect electrical clearance, impedance, creepage, and signal-integrity requirements.

PCB warpage comparison showing asymmetric stackup and uneven copper versus symmetric stackup and balanced copper

How Can PCB Bow and Twist Be Reduced Before Fabrication?

The most effective time to control PCB warpage is before the stackup and panel design are frozen.

Useful DFM checks include:

  • Keep the multilayer stackup symmetric around the centerline.
  • Use matching copper weights on mirrored layers where practical.
  • Balance copper coverage across opposing sides.
  • Review large copper-free or low-density regions.
  • Keep core and prepreg construction mechanically balanced.
  • Review glass orientation where material construction makes it relevant.
  • Consider board thickness relative to size and mechanical support.
  • Balance copper in panel rails and breakaway areas.
  • Review mixed-material stackups for CTE and lamination compatibility.
  • Define any tighter flatness requirement on the drawing before production.

For EBest Circuit projects, bow-and-twist risk can be reviewed during DFM together with stackup construction, copper distribution, panelization, material selection, and finished thickness.

How Is Bow and Twist Controlled During PCB Manufacturing?

Manufacturing control focuses on preventing uneven stress from being built into or released from the panel.

Important process controls include:

  • Laminate and prepreg storage
  • Glass direction and ply construction
  • Controlled lamination temperature and pressure
  • Resin-flow and cure control
  • Symmetrical panel construction
  • Copper plating balance
  • Solder-mask and legend curing
  • HASL or other high-temperature processing
  • Panel support during handling
  • Controlled cooling
  • Final flatness inspection

Lamination is particularly important because once intrinsic deformation is locked into the multilayer structure, later flattening may not provide a permanent correction.

Final inspection should be performed on the board in the required delivered form and against the applicable customer or IPC limit.

When Should a PCB Use a Tighter Flatness Limit Than IPC 0.75%?

A tighter requirement may be appropriate whenever the standard 0.75% bare-board limit does not provide enough mechanical or assembly margin.

Examples include boards with:

  • Large BGA or fine-pitch area-array packages
  • Long board-edge connectors
  • Press-fit connector fields
  • Tight card-guide or chassis interfaces
  • Thin, large-format PCBs
  • High-density SMT on both sides
  • Precision optical or sensor assemblies
  • Customer-defined coplanarity requirements

The correct tighter value depends on the product. It should not be assumed that every BGA board requires 0.5%, 0.3%, or another generic number.

IPC-6012F allows procurement documentation to specify requirements other than the default 0.75% or 1.5% limits.

For tight-flatness projects, the designer and PCB manufacturer should agree on the measurement method, delivery form, panel condition, temperature condition, and acceptance limit before fabrication.

Does IPC-TM-650 Bow and Twist Apply to an Assembled PCBA?

IPC-TM-650 2.4.22 is primarily a bare printed-board flatness test. Its scope covers individual rigid boards, rigid portions of rigid-flex boards, and multiple-board panels, but it does not address all special conditions of populated assemblies such as component weight, placement, edge supports, and connectors.

An assembled PCBA can behave differently because reflow temperature, component packages, heat sinks, connectors, fixtures, and solder joints all influence deformation.

For temperature-dependent board flatness, separate methods may be used to evaluate local board shape through a simulated reflow cycle. These do not replace room-temperature bow and twist inspection of the bare PCB.

Bare-board bow/twist and assembled-PCBA warpage should therefore be treated as related but different engineering problems.

FAQ About PCB Bow and Twist

1. What is the maximum PCB bow and twist allowed by IPC?
IPC-6012F specifies a default maximum of 0.75% for printed boards using surface-mount components and 1.5% for other printed boards, unless procurement documentation requires a different limit.

2. How is PCB bow percentage calculated?
PCB bow percentage is calculated from the maximum measured gap relative to the corresponding board length or width.

3. How is PCB twist percentage calculated?
PCB twist percentage is calculated from the raised-corner gap and the PCB diagonal using the IPC-TM-650 production method.

4. Is PCB bow the same as PCB twist?
No. Bow is a curved deformation in which the four corners can remain coplanar, while twist is a diagonal deformation that raises one corner relative to the other three.

5. What commonly causes excessive PCB warpage?
Asymmetric stackups, uneven copper distribution, material construction, lamination stress, incomplete cure, mechanical handling, and later thermal processes can all contribute.

6. Can a customer specify a tighter bow and twist limit?
Yes. A customer can define a tighter requirement in the procurement documentation, and that agreed requirement takes precedence over the general IPC default for the project.

PCB bow and twist should be controlled from stackup design through final inspection rather than treated only as an end-of-line flatness problem. Symmetry, copper balance, material construction, lamination, panel design, and thermal processing all influence the final result.

For PCB projects with tight flatness requirements, EBest Circuit can review the Gerber files, stackup, copper distribution, panelization, finished thickness, assembly requirements, and target bow/twist limit before production. Send the project data to sales@bestpcbs.com for DFM review.

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What Is Sequential Lamination in PCB and How Does It Work?

September 17th, 2026

Sequential lamination builds a PCB in two or more controlled lamination stages so internal vias can be formed before later layers make them inaccessible. The practical question is not how many layers the board has. It is which blind, buried, or microvia connections must be completed at each stage and what those choices mean for reliability, cost, and lead time.

sequential lamination, multilayer PCB cross-section beneath a lamination press

What Is Sequential Lamination in PCB?

A conventional multilayer PCB is usually bonded as one prepared stack. Sequential lamination pauses the build, forms connections in an accessible partial structure, adds another layer set, and continues outward.

A buried via can therefore be drilled and plated before later layers enclose it. Multi-level microvias follow the same logic: each lower tier is completed before the next dielectric covers its landing layer.

The deciding test is layer access. Trace every via from its drilling side to its target layer. If that connection can still be formed after the main bond, another build stage may be unnecessary. If the target becomes enclosed first, the stack must be divided into accessible substructures. Sequential lamination is therefore a construction sequence, not a performance grade.

How Is Sequential Lamination Different From Standard PCB Lamination?

The difference is when the internal connections are made. Standard construction completes most internal preparation before one main multilayer bonding stage. Sequential construction inserts drilling, plating, filling, or inspection between bonding stages.

Factor Standard Multilayer Lamination Sequential Lamination
Lamination process Mainly one multilayer bonding stage Two or more controlled build stages
Via structures Mainly through vias and structures accessible after bonding Buried vias, blind vias, and multi-level microvias
Layer access Internal layers become inaccessible after bonding Selected layers remain accessible between stages
Process complexity Lower when it meets the design Higher because controlled operations repeat
Cost and lead time Generally lower Generally higher
Typical use Conventional multilayer PCB HDI and complex internal via structures

A high layer count does not by itself require sequential lamination. A board with many layers and only plated through holes may use a conventional build, while a board with fewer layers but a buried via or several microvia tiers may need staged construction.

When Does a PCB Design Require Sequential Lamination?

Sequential lamination becomes necessary when a required connection cannot be drilled, plated, filled, or verified after the full stack has been bonded. Four design situations commonly create that condition:

  • Buried vias that would be sealed inside the finished stack: the via must be completed in a core or sub-composite while both target layers are still exposed.
  • Multiple HDI build-up layers: each added dielectric can create a new microvia level that must be formed before another layer is added.
  • Stacked or multi-level microvias: the lower microvia usually needs controlled plating, filling, and a planar landing surface before the upper level is built.
  • Fine-pitch BGA escape that cannot reasonably use through vias: adjacent-layer microvias can release routing area, but their start and stop layers determine the build sequence.

High layer count and the HDI label are not sufficient reasons by themselves. Hide the outer layers in the stackup view, add them back in build order, and note where a connection loses access before it is complete. That via map reveals whether staged construction is necessary and whether a routing change could remove a build-up tier.

How Does the Sequential Lamination Process Work?

The process follows the changing access to each via target. It starts with the innermost structure, adds a layer set, completes the connections that are accessible at that point, and repeats only when the stackup requires another tier.

sequential lamination, six-stage PCB build sequence on a white background
  1. Document the stackup and via spans. Identify every copper layer, dielectric, via start and stop layer, fill requirement, and controlled-impedance reference. The output is a build diagram that can be checked before routing is frozen.
  2. Build the initial core or sub-composite. Image and etch the inner copper, then align the partial structure. The layers that will support internal vias remain reachable.
  3. Drill and plate the internal vias. Form the buried holes or first accessible connections, then clean, metallize, fill, and inspect them as required. Their conductive path is complete before enclosure.
  4. Laminate the next layer pair or build-up layer. Add dielectric and copper to the verified partial structure. The result is a larger stack with a new outer surface available for processing.
  5. Form the next blind or microvia level. Drill and plate the newly accessible tier, using filling or planarization where another via must land above it. This completes the next connection level.
  6. Repeat as required and finish the PCB. Continue the add-layer-and-connect sequence for the remaining tiers, then complete final through holes, outer-layer processing, solder mask, finish, profiling, and the agreed testing.

This sequence explains the design consequence: adding or extending one via span can change the required build stages. It may add a fill dependency, alter which layer must remain exposed, or require another controlled cycle.

For the designer, the useful output is a confirmed build diagram: layer order, via levels completed at each stage, landing surfaces required by the next tier, and any geometry or material limit that changes the stackup.

How Do Different Via Structures Affect the Lamination Sequence?

Each via must be formed while its drilling side and target layer are accessible. The name of the via helps describe the connection, but the exact start-stop layers and stacking arrangement determine the sequence.

sequential lamination, cross-sections of through blind buried stacked and staggered vias
  • Through vias: these normally pass through the completed stack and can be drilled after final lamination, so they do not create a sequential stage by themselves.
  • Buried vias: these connect internal layers and must be processed before later layers hide both ends.
  • Blind vias: these connect an outer surface to an internal target. Their route depends on the depth, dielectric thickness, drill method, and stage at which the target is exposed.
  • Single-level microvias: these usually connect adjacent layers through a thin dielectric and may fit within one build-up stage.
  • Stacked microvias: the upper microvia lands directly above the lower one, creating a fill and planarity dependency between tiers.
  • Staggered microvias: the levels are offset, which avoids a direct via-on-via interface but does not necessarily remove the need to build each dielectric tier in sequence.

Do not assign a cycle count from terms such as blind via or HDI alone. Two boards can use the same via label yet require different sequences because the vias stop on different layers or use different fill and stacking arrangements.

How Does the PCB Stackup Determine the Number of Lamination Cycles?

The cycle count follows the number of connection groups that must be completed before another layer blocks access. Total layer count matters less than the order in which via targets disappear inside the stack.

Notation such as 1+N+1 or 2+N+2 shows the build-up layers around a core region, but it does not prove a universal press count. The core may contain buried vias, and outer tiers may be stacked, staggered, symmetric, or one-sided. The notation shows the layer arrangement; the via start-stop map shows the build dependencies.

Three simplified cases show how that logic changes the build:

  • Eight-layer board with through vias only: the prepared layers can normally be bonded in the main multilayer lamination, followed by through-hole drilling. The layer count does not create another stage by itself.
  • Core containing buried vias: the internal via is drilled and plated while its core or sub-composite is accessible. Outer layers are laminated only after that connection is complete, so the via architecture creates a staged build.
  • 2+N+2 HDI with stacked microvias: the first microvia tier must be formed before the second build-up dielectric covers it. Direct stacking can also require a filled, planar lower via before the upper tier is added.

Estimate the sequence from the inside out:

  1. Map every start and stop layer. Separate through, blind, buried, and microvia spans.
  2. Group connections that are accessible together. Vias that can be formed in the same exposed sub-composite may share a stage.
  3. Mark each covering event. When a new dielectric hides a completed target, record the lamination needed before that happens.
  4. Add stacking dependencies. A microvia tier that needs a filled, planar lower via must be completed before the next tier can begin.

If two proposed builds show different cycle counts, compare their layer-by-layer diagrams, via formation stages, and fill sequence before treating either number as correct.

What Should You Check Before Finalizing a Sequential Lamination Stackup?

Review the stackup before dense routing makes the construction difficult to change. The goal is to prove that every added tier solves a real routing or electrical constraint and that its build dependency is understood.

  • Via start and stop layers: make the CAD data, drill table, and cross-sectional stackup agree.
  • Stacked or staggered arrangement: confirm whether direct stacking is necessary or an offset path can meet routing and reliability needs.
  • Number of build-up tiers: test whether a routing change, another conventional layer, or a different escape pattern can remove a tier.
  • Material system: check whether cores, prepregs, build-up dielectrics, and copper constructions suit the planned press and assembly thermal history.
  • Impedance and reference layers: protect return paths, reference-plane continuity, dielectric targets, and any backdrill requirement when the build changes.
  • Reliability requirements: state the product environment, assembly exposure, acceptance class, coupon needs, and qualification expectations.

Generic online limits should not be copied directly into CAD rules. Usable geometry depends on the material, dielectric thickness, copper, drill and fill process, registration capability, and product requirement. For a useful DFM or quotation review, send the stackup, via map, fabrication data, quantity, and reliability requirements together.

How Can Multiple Lamination Cycles Affect PCB Reliability?

Extra cycles add thermal, pressure, and registration exposure. That does not make a sequentially laminated PCB unreliable by definition, but it reduces the value of judging the design by layer count or a room-temperature electrical test alone.

Risk area Why multiple cycles matter What to verify
Microvia interface Repeated thermal exposure can reveal weak plating, fill, or target-pad interfaces Via structure, fill route, representative coupons, and qualification method
Layer registration Alignment error can accumulate as more structures are bonded Capture pads, registration allowance, and evidence from intermediate stages
Material thermal history The laminate experiences repeated heat and pressure before assembly reflow Material suitability for the full fabrication and assembly history

Risk is often concentrated at interfaces: a microvia base meeting its target pad, a filled via supporting an upper tier, or resin bonding around uneven copper. Residue, voids, weak plating, poor planarity, expansion mismatch, and registration error can reduce margin during reflow or thermal cycling.

Qualification should represent the connections with the greatest structural dependency. Match the coupon or test vehicle to the microvia tiers, target-pad interfaces, fill arrangement, materials, and expected assembly exposure. A room-temperature continuity check confirms a path at that moment; it does not reproduce repeated reflow or service thermal cycling.

How Does Sequential Lamination Affect PCB Cost and Lead Time?

Cost and lead time usually rise because pressing, drilling, plating, filling, planarization, and inspection may repeat for each build stage. There is no reliable universal percentage; the impact depends on the stackup, material, panel use, via density, registration demand, testing, and quantity.

  • Repeated controlled operations: each added tier consumes equipment time and requires another alignment and processing sequence.
  • Fill and planarization: stacked structures may need a prepared landing surface before the next level can be formed.
  • Intermediate verification: hidden circuitry and via quality need to be checked before the next layer removes access.
  • Longer dependency chain: later work cannot begin until the preceding structure is complete and suitable for the next tier.
  • Greater late-stage loss: a defect found after several completed stages affects more accumulated processing than an early defect.

The best cost reduction is often one unnecessary build-up tier removed before layout release. Compare alternatives that preserve the same electrical and mechanical requirements, such as fewer unique via spans, staggered rather than stacked microvias, a different BGA escape, or an added conventional layer.

FAQs About Sequential Lamination Technology

Q1: What files help a supplier quote the actual build instead of making assumptions?

A1: Send one consistent data package. Include Gerber or ODB++ data, NC drill data, a controlled stackup, via start-stop layers, finished copper weights and board thickness, material and impedance requirements, via-fill or cap requirements, acceptance and test expectations, quantity, and target delivery date.

Q2: How should blind and buried via spans appear in the drill data?

A2: Every start-stop layer pair must be unambiguous. Separate drill files or a clearly mapped drill table can be used, but each span should identify its layer pair, plated status, finished size, tolerance, and any fill or cap requirement. The naming convention matters less than agreement between the drill data, stackup, and fabrication drawing.

Q3: Can stacked microvias be changed to staggered microvias without design approval?

A3: No. The alternative may improve the build margin, but it changes pad locations, routing space, and possibly reference-plane or impedance conditions. It should be proposed as a documented DFM change and approved in the controlled design data before production.

Q4: Why can two PCB quotations use different build sequences?

A4: The suppliers may be working from different assumptions or grouping operations differently. Compare the annotated build diagrams, via spans, fill and planarization route, materials, impedance construction, and test scope. A lower cycle number is not automatically the better or equivalent proposal.

Q5: Can an enclosed buried-via defect be repaired after final lamination?

A5: It is generally not a practical local rework. The connection is trapped inside the bonded stack, so opening it can damage surrounding layers and dielectric. Intermediate inspection, representative coupons, and final electrical testing are used to find problems; an affected bare board is usually rejected or rebuilt rather than patched.

Ready to build a sequential-lamination PCB? Send your stackup, Gerber or ODB++ files, via map, material and impedance requirements, quantity, and target delivery date to sales@bestpcbs.com. EBest Circuit can review the proposed construction and prepare a PCB quotation based on the actual build sequence.

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What Is Brazing? Process, Types, Uses & Welding vs Soldering

September 17th, 2026

What is brazing? It joins metal parts without melting the base materials themselves. Instead, heat melts a separate filler alloy, which wets the mating surfaces and flows through the joint gap by capillary action. After cooling, the filler solidifies and forms a metallurgical bond between the parts.

This process is useful when welding would create too much distortion, when dissimilar metals need to be joined, or when a clean and leak-tight joint is required. Brazing is common in HVAC, refrigeration, automotive, aerospace, electrical equipment, heat exchangers, tooling, and many other metal assemblies.

What is brazing illustration showing torch brazing of copper tubing and filler metal flowing into the joint

Key Takeaways

  • Brazing is a metal-joining process that melts a filler metal above 450°C (840°F) while keeping the base metals solid.
  • The molten filler enters a close-fitting joint through wetting and capillary action, rather than by melting the parts being joined.
  • Successful brazing depends heavily on clean surfaces, correct joint clearance, suitable filler metal, controlled heating, and oxide management.
  • Brazing differs from welding because the base metal normally does not melt. It differs from soldering mainly because brazing filler metals melt above 450°C.
  • Common methods include torch, furnace, induction, resistance, dip, and vacuum brazing.
  • Brazing is widely used for HVAC tubing, heat exchangers, automotive assemblies, aerospace parts, electrical contacts, cutting tools, and leak-tight metal joints.
  • Copper-to-copper joints can sometimes use phosphorus-bearing filler without separate flux, while dissimilar joints require more careful filler and flux selection.

What Is Brazing?

Brazing is a metal-joining process in which a filler metal melts above 450°C (840°F) and flows between closely fitted parts while the base metals remain solid.

The process uses heat to bring the joint area above the filler alloy’s melting range, but below the melting temperature of the components being joined. The filler then wets the surfaces and fills the gap between them.

This makes brazing different from welding, where the base material is normally melted to create the joint. It also separates brazing from soldering, which uses filler metals with a liquidus temperature below 450°C.

A brazed joint can connect similar or dissimilar metals, depending on the filler alloy, joint design, surface condition, and service requirements.

How Does the Brazing Process Work?

The answer to what is brazing process is straightforward: heat a prepared joint until the filler metal melts and flows through the clearance between the parts.

  1. Clean the surfaces. Remove oil, grease, dirt, and oxides that could prevent wetting.
  2. Fit the parts together. Maintain an appropriate and reasonably uniform joint clearance.
  3. Apply flux if required. Flux limits oxide formation and helps the molten filler wet the surfaces.
  4. Heat the joint. Bring the assembly to the correct brazing temperature without melting the base metals.
  5. Introduce the filler metal. The filler melts when it contacts the heated joint area.
  6. Allow capillary action to distribute the filler. Molten alloy is drawn into the joint.
  7. Cool the assembly. The filler solidifies and forms the final bond.
  8. Clean the joint if necessary. Residual flux may need to be removed.

The filler should generally melt because of heat in the workpieces rather than being melted directly by the flame. This helps produce more uniform flow and reduces the risk of overheating the filler before the joint reaches brazing temperature.

Brazing process steps showing cleaning fit-up flux heating filler application and cooling

Why Are Joint Clearance, Wetting and Capillary Action Important?

A brazed joint depends on molten filler being able to wet both surfaces and flow through the joint gap. Joint clearance therefore has a direct effect on filler distribution.

If the gap is too large, capillary attraction becomes weaker and the filler may not fill the joint evenly. If the gap is too tight, filler penetration can also be restricted, especially when thermal expansion changes the clearance during heating.

Good wetting also requires clean metal surfaces. Oil, heavy oxidation, or unsuitable surface films can prevent the filler from spreading across the base metal.

Clean surface + suitable clearance + correct temperature → good wetting → capillary flow → complete joint

This is one reason brazing quality cannot be judged only by how much filler is visible around the outside of the connection. A large external fillet does not automatically mean the filler has properly penetrated the internal joint.

Brazing wetting and capillary action diagram showing correct clearance too wide and too tight joints

What Are Brazing Rods, Filler Metals and Flux?

Brazing filler metal is the alloy that melts and forms the joint between the base materials. A brazing rod is simply one physical form in which that filler can be supplied.

Common filler forms include:

  • Rod
  • Wire
  • Ring
  • Strip
  • Foil
  • Preform
  • Paste
  • Powder

Different filler alloys are selected according to the base metals, brazing temperature, corrosion requirements, service temperature, joint strength, and manufacturing process.

Flux serves a different purpose. It helps control oxides that would otherwise prevent proper wetting and filler flow. Depending on the formulation, flux can dissolve existing oxides and reduce further oxidation during heating.

Not every brazing operation requires external flux. Vacuum brazing and controlled-atmosphere processes can manage oxidation without conventional flux, while some copper-phosphorus fillers can be self-fluxing on copper-to-copper joints.

Brazing filler metal forms including rod wire ring paste powder and brazing flux

What Types of Brazing Are There?

Brazing methods are usually classified by how heat is applied to the joint.

Brazing Method Heat Source / Environment Typical Use
Torch brazing Gas flame HVAC, repair, low-volume production
Furnace brazing Controlled furnace Batch or volume assemblies
Induction brazing Electromagnetic induction Fast, localized heating
Resistance brazing Electrical resistance Small, repeatable joints
Dip brazing Molten bath Specialized assemblies
Vacuum brazing Vacuum furnace Clean, high-reliability components

Torch brazing is common for manual work because the heat can be directed at a specific joint. HVAC copper tubing is a typical example.

Furnace brazing is useful when many joints must be heated at once. It provides better repeatability and lends itself to higher-volume manufacturing.

Induction brazing heats conductive parts rapidly using an alternating electromagnetic field. It is useful where short cycle times and local heat control matter.

Vacuum brazing is used when oxidation, contamination, flux residue, or high joint cleanliness are critical, such as in aerospace, vacuum hardware, and precision assemblies.

Types of brazing including torch furnace induction resistance and vacuum brazing

Brazing vs Welding: What Is the Difference?

The most important difference is that brazing normally does not melt the base metals, while welding usually joins parts by locally melting and fusing the base material.

Factor Brazing Welding
Base metal melts No Usually yes
Filler metal Commonly required Depends on process
Joint mechanism Wetting and capillary flow Fusion
Heat input to base material Usually lower Usually higher
Distortion Often lower Often higher
Dissimilar metals Often easier Can be more difficult
Joint design Often relies on overlap Butt, fillet, lap and other joints

Brazing is useful when dimensional stability matters because the base parts remain below their melting temperature. This can reduce distortion and preserve more of the original component geometry.

Welding is often preferred when a fused structural joint is required or when the joint must become part of the base-metal section itself.

It is not accurate to say that welding is always stronger than brazing. Joint strength depends on material combination, filler alloy, joint overlap, clearance, section thickness, loading direction, and operating temperature.

Brazing vs Soldering: What Is the Difference?

Brazing and soldering are closely related because both join materials using a molten filler while keeping the base metals solid.

The standard temperature distinction is the filler metal’s liquidus temperature:

  • Brazing: above 450°C / 840°F
  • Soldering: below 450°C / 840°F
Factor Brazing Soldering
Base metal melts No No
Filler temperature Above 450°C Below 450°C
Capillary action Common Common
Flux may be used Yes Yes
Typical mechanical capability Higher Lower
Typical service temperature Higher Lower
Common examples HVAC, heat exchangers, tooling Electronics, wires, connectors

Soldering is especially common in electronics because the lower temperature limits thermal stress on components and PCB materials used in PCBA.

Brazing is more appropriate when higher mechanical strength, higher service temperature, leak-tight tubing, or more demanding metal assemblies are required.

Brazing welding and soldering comparison showing base metal condition filler behavior and temperature ranges

What Metals Can Be Brazed?

Many common engineering metals can be brazed when a compatible filler alloy and process are selected.

Examples include:

  • Copper
  • Brass
  • Carbon steel
  • Stainless steel
  • Nickel and nickel alloys
  • Aluminum
  • Silver-containing alloys
  • Carbide-to-steel tool assemblies
  • Selected dissimilar-metal combinations

Copper is particularly brazing-friendly because many filler alloys wet it effectively, and copper tubing can be joined reliably with proper preparation.

Aluminum also can be brazed, but its stable oxide layer requires suitable flux, atmosphere, filler alloy, and temperature control.

The key point is that brazability depends on the specific base-metal combination, not just on whether each material can be brazed individually.

What Is Brazing Used For?

Brazing is used when metal components need a strong, clean, dimensionally stable, or leak-tight joint without melting the base materials.

Common applications include:

  • HVAC refrigeration lines
  • Copper tubing
  • Heat exchangers
  • Radiators
  • Automotive components
  • Aerospace assemblies
  • Cutting tools
  • Carbide tips
  • Electrical contacts
  • Hermetic housings
  • Plumbing assemblies
  • Industrial tubing
  • Refrigeration equipment
  • Vacuum hardware

Heat exchangers are a good example because many thin metal sections and internal flow passages may need to be joined while maintaining geometry and leak tightness.

Cutting tools also use brazing to attach carbide inserts or tips to steel bodies. The process allows materials with very different properties to be joined without melting either base component.

Industrial brazing applications including HVAC heat exchanger cutting tool and electrical contact

What Is Brazing in HVAC and Copper Pipe Work?

In HVAC and refrigeration systems, brazing is widely used to join copper tubing that carries refrigerant under pressure.

The process is preferred because properly brazed joints can provide:

  • Strong mechanical connection
  • Leak resistance
  • High-pressure capability
  • Good temperature resistance
  • Compact joint geometry

For copper-to-copper tubing, phosphorus-bearing copper filler alloys are commonly used. Some of these fillers can provide self-fluxing action on clean copper, so separate flux may not always be required.

For copper-to-brass, the filler and flux requirements depend on the alloy system and joint design.

For copper-to-steel, more care is required. Phosphorus-bearing filler metals should not simply be transferred from copper-to-copper practice because brittle compounds can form with ferrous materials. A suitable phosphorus-free filler and compatible flux are normally selected instead.

HVAC brazing quality also depends on tube preparation, fit-up, heating technique, filler distribution, and oxidation control inside and outside the tubing.

HVAC brazing copper refrigerant line with copper-to-copper and copper-to-steel joint examples

What Are the Advantages and Limitations of Brazing?

Brazing offers several manufacturing advantages, but it also places tight requirements on surface condition and joint design.

Advantages Limitations
Lower distortion than many welding processes Joint clearance is important
Joins dissimilar metals Surface cleanliness is critical
Good for thin sections Filler compatibility must be verified
Can create leak-tight joints Service temperature is limited by filler alloy
Suitable for complex assemblies Flux residues may require cleaning
Can be automated Poor joint design can reduce strength
Base metals remain solid Heating must still be controlled

Because the base metals do not melt, brazing can preserve thin sections and precision geometries better than some fusion processes.

The trade-off is that brazing is less forgiving of contaminated surfaces, unsuitable clearances, or incorrect alloy selection. A visually neat joint can still perform poorly if filler has not penetrated the intended joint area.

FAQ About Brazing

1. What temperature is considered brazing?
Brazing uses filler metals with a liquidus temperature above 450°C (840°F) while remaining below the melting temperature of the base metals.

2. Does brazing melt the base metal?
No. The base metals remain solid during brazing. Only the filler metal is melted and distributed through the joint.

3. Is brazing stronger than soldering?
Brazed joints generally support higher mechanical loads and service temperatures than soldered joints, but actual strength depends on the filler alloy, base materials, clearance, joint geometry, and loading.

4. Can copper be brazed?
Yes. Copper is commonly brazed in HVAC, refrigeration, plumbing, heat exchangers, and electrical assemblies.

5. Does copper brazing need flux?
Not always. Certain phosphorus-bearing filler metals are self-fluxing on copper-to-copper joints, although other material combinations may require flux.

6. Is brazing the same as welding?
No. Welding normally melts and fuses the base material, while brazing joins solid base metals using a separate molten filler.

Brazing is most successful when the filler alloy, flux or atmosphere, joint clearance, and heating method are selected as one system rather than as separate choices. For engineering projects, the base-metal combination and service conditions should always be defined before choosing the brazing process.

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How Do You Control PCB Surface Flatness?

September 17th, 2026

PCB surface flatness describes how closely a bare board or a defined local area conforms to its intended plane. For fabrication acceptance, bow and twist are the usual whole-board measures; for assembly, local coplanarity near a BGA, connector, thermal interface or test fixture may be just as important. At EBest Circuit (Best Technology), we control flatness through stack-up review, copper balance, lamination, panel design, routing and dimensional inspection, then align the acceptance method with your drawing and assembly process.

Conceptual PCB surface flatness inspection with a height gauge and optical metrology system

What Does PCB Surface Flatness Mean?

PCB flatness is not a single universal reading. A finished board can meet a bow-and-twist limit and still have a local high point that interferes with a heatsink, connector or fine-pitch package. Conversely, a small local feature may be acceptable even when a poorly supported panel appears distorted during handling. The specification must identify the object, area, condition and measurement method.

A flat surface PCB requirement should therefore answer four questions: Is the sample a production panel, a routed bare board or an assembled board? Is the concern global bow and twist or local surface profile? Is the measurement made at room temperature or through a thermal cycle? Which datum, fixture and acceptance limit apply?

Do not confuse PCB surface flatness with PCB surface roughness. Roughness describes small-scale texture, while flatness concerns form over a much larger area. PCB surface finish also affects pad planarity and solderability, but an ENIG or OSP coating cannot correct a warped laminate.

PCB Bow, Twist and Local Coplanarity: What Is the Difference?

Bow is a roughly cylindrical or spherical curvature in which the corners of a rectangular board remain in one plane. Twist is diagonal deformation: three corners can touch a reference plane while the fourth is raised. Local coplanarity describes height variation within a defined region, such as a BGA land field or the mounting area for a power module.

Conceptual comparison of PCB bow and PCB twist against a flat reference plane
Condition What changes Useful measurement basis
Bow The board curves along its length or width while the corners remain approximately coplanar Maximum gap divided by the relevant board dimension
Twist One corner rises relative to the plane formed by the other three corners Corner displacement and diagonal length using the specified method
Local coplanarity A defined pad, component or mounting region departs from its local datum plane Profile map, CMM or optical measurement over the stated area
Dynamic warpage Board shape changes as temperature changes Thermal-profile measurement with the agreed support condition

The phrase PCB warpage is often used broadly for bow, twist and temperature-dependent shape change. A PCB bow and twist specification is appropriate for room-temperature bare-board acceptance, but it should not be treated as proof of local BGA coplanarity or behavior during reflow.

Why Does Flatness Matter During PCB Assembly?

Assembly equipment assumes a predictable relationship between the board, stencil, placement head and support system. Excessive deformation can reduce contact between the stencil and pads, change solder-paste release, shift the focal plane for inspection, or leave a large package with uneven stand-off. Press-fit connectors, edge-card contacts and enclosure features can also become difficult to align.

Conceptual illustration of PCB flatness effects on stencil contact, BGA coplanarity and fixture support

For fine-pitch assemblies, our HDI PCB manufacturing and PCB assembly services can be reviewed together. The board construction, solder-paste process, package coplanarity and underside support all affect the result. A flat bare board does not eliminate every assembly variable, and a fixture that forces a board flat can hide its free-state deformation.

Mechanical interfaces create another constraint. If a PCB must contact a thermal pad or metal baseplate, the drawing should define the mounting region and allowable gap rather than relying on a general statement such as “board must be flat.”

How Is PCB Flatness Measured?

A basic PCB flatness measurement places the bare board on a precision surface plate and uses feeler gauges, a height indicator or equivalent metrology to measure the gap. IPC-TM-650 Method 2.4.22 describes production and referee procedures for bow and twist percentage on rigid boards, rigid portions of rigid-flex boards and panels. Its scope does not establish the special support conditions needed for populated assemblies.

Measurement task Typical equipment Report should record
Go/no-go bow check Surface plate and calculated feeler or pin gauge Board length/width, permitted percentage and tested direction
Actual bow percentage Surface plate, gauge set and dimensional measurement Maximum gap, corresponding span and calculated result
Twist measurement Surface plate, corner support and height gauge Diagonal, raised-corner displacement and calculation method
Local surface profile CMM, laser scanner or optical metrology Datum, area of interest, point spacing and maximum deviation
Thermal warpage Temperature-controlled optical measurement system Temperature profile, support, side viewed and shape versus time

For bow, the percentage is the maximum gap divided by the measured length or width, multiplied by 100. Under the production twist method in IPC-TM-650 2.4.22, twist percentage is the measured raised-corner gap divided by twice the diagonal, multiplied by 100. A PCB bow and twist formula must therefore match the selected procedure. A PCB bow and twist calculator is only as reliable as its inputs; using the wrong span or fixture creates a precise-looking but invalid result.

Record the board dimensions, diagonal, measured gap, test side and restraint used for every PCB bow and twist measurement. This is more useful than reporting only a pass/fail label because it makes the result reproducible.

A documented PCB surface flatness check should also identify whether protective films, tooling tabs or breakaway rails remain on the sample. If measurements from the fabricator and assembler disagree, first compare sample state, reference plane, restraint and temperature before comparing numbers.

Which Flatness Limits Should You Put on the Fabrication Drawing?

A PCB flatness specification should state the controlling document and revision, product class where applicable, maximum bow and twist, test condition, sample state and any local coplanarity zone. A PCB flatness tolerance is meaningful only when those conditions are defined. “Meet IPC” alone is incomplete because several IPC documents address different products, methods and acceptance contexts.

For our FR4 boards, we list a bow-and-twist capability of ≤0.75%, subject to the stack-up, board size, thickness, material system, copper distribution and engineering review. This is a manufacturing capability statement, not an automatic limit for every design. A thin, long board, a mixed-material stack-up or a local interface may need a different requirement and a dedicated measurement plan.

Drawing item Example of a clear instruction Why it matters
Sample state Routed bare board after final finish, rails removed Prevents panel rails from masking individual-board shape
Global requirement Maximum bow and twist per the named method and agreed percentage Defines the overall acceptance calculation
Local requirement Maximum plane deviation within a marked component or mounting area Protects the interface that drives assembly performance
Thermal condition Room temperature or specified temperature profile Separates incoming inspection from reflow behavior
Reporting Lot sample size, datum, instrument and measured result Makes supplier and customer data comparable

IPC-6012 bow and twist requirements should be interpreted with the purchase documentation and applicable revision. If your product has a tighter enclosure, optics or thermal-interface requirement, put that requirement on the drawing instead of expecting the general board class to imply it.

What Causes PCB Warpage?

PCB warpage develops when stresses are not balanced through the board thickness or across the panel. Laminate resin, glass reinforcement, copper and surface coatings expand and contract differently. Lamination, oxide treatment, solder-mask curing, surface finishing and assembly reflow expose the construction to repeated heat and moisture changes.

  • Asymmetric stack-up: different dielectric thicknesses or copper weights above and below the centerline create unequal shrinkage.
  • Uneven copper distribution: a solid plane on one side and sparse routing on the opposite side can leave residual stress after cooling.
  • Material mismatch: hybrid high-frequency, metal-core or stiffener constructions can respond differently to temperature.
  • Thin or elongated geometry: low bending stiffness makes the same residual stress produce more visible deflection.
  • Panel and routing design: weak rails, uneven coupon placement, large cutouts and an unbalanced routing sequence can release stress unevenly.
  • Moisture and thermal history: storage, baking, solder-mask cure and reflow can change the free-state shape.

A PCB warpage calculation based only on laminate CTE cannot predict the final board. Copper pattern, resin flow, press cycle, panel position, routing and later assembly loads also matter. Use calculation to compare design options, then validate critical builds with representative coupons or samples.

How Do Stack-Up Symmetry and Copper Balance Reduce Warpage?

A mechanically balanced stack places similar copper weights and dielectric structures at comparable distances from the centerline. It does not require identical routing on every layer, but it avoids unnecessary imbalance in copper area and layer construction. This gives the laminate a more uniform response during pressing and cooling.

Conceptual PCB stack-up comparison showing balanced and unbalanced copper distribution

Our FR4 PCB manufacturing supports single-sided, double-sided and multilayer constructions up to 32 layers, subject to engineering review. More layers do not automatically improve or reduce flatness. What matters is the actual build: core and prepreg selection, copper weight, layer pairing, resin fill, overall thickness and panel utilization.

Copper thieving can improve local plating distribution and may help balance unused panel areas, but it is not a universal repair for an asymmetric product stack-up. We review copper distribution together with impedance, spacing and manufacturability so a flatness correction does not create an electrical or fabrication problem elsewhere.

How Do Board Thickness, Panelization and Routing Affect Flatness?

Thickness raises bending stiffness, so very thin boards are more sensitive to handling and residual stress. Our extra-thin PCB options include constructions from 0.15 mm, subject to material, size and engineering review. A thin-board requirement should therefore include panel support, assembly fixture and handling expectations rather than only the nominal thickness.

Panelization affects flatness before and after separation. Rails, crossbars, breakaway tabs, V-scores, routed slots and coupon placement change panel stiffness and the way stress is released. A large panel can pass while restrained by its frame, yet individual boards may change shape after routing. For flatness-critical parts, inspect both the production panel and the final routed board when those states serve different purposes.

Board outline matters too. Long narrow shapes, large internal windows and one-sided edge copper can create compliant regions. The best corrective action may be a stack-up change, panel rotation, added temporary support or revised routing sequence; simply increasing the final thickness can conflict with connectors, impedance or enclosure space.

Can PCB Surface Finish Improve Flatness?

A PCB surface finish can improve pad planarity relative to another finish, but it does not make the entire laminate flat. ENIG and immersion finishes deposit a comparatively uniform coating on exposed copper, while HASL can leave more variation across individual pads. This distinction matters for fine-pitch solder printing and probing.

However, the phrase PCB surface finish flat surface should not be interpreted as an overall warpage control method. Finish thickness is small compared with the board stack, and the chemical or thermal process cannot reverse a mechanically unbalanced construction. Select the finish for solderability, contact function, wire bonding, shelf life and pad-planarity needs; control global shape through the board design and fabrication process.

How Do We Control Flatness During PCB Manufacturing?

We begin with the released stack-up and panel, because most flatness risks are easier to prevent than to sort after fabrication. Our DFM review looks for asymmetry, concentrated copper, thin long geometry, mixed materials, large openings, unusual routing and local interfaces that deserve their own tolerance.

  1. Confirm the applicable flatness definition, acceptance method and sample state.
  2. Review layer symmetry, dielectric distribution and copper balance.
  3. Plan panel rails, coupons, scoring or routing so the panel remains stable during processing.
  4. Control lamination, curing and cooling according to the approved material and stack-up.
  5. Inspect at the state that matters: panel, routed bare board and, when separately agreed, the assembly condition.
  6. Use dimensional data to distinguish a design-driven pattern from a process or handling issue.

Our listed quality capabilities include 3D dimensional measurement, AOI, microsection analysis and electrical testing. These tools answer different questions. Flatness metrology measures shape; electrical testing checks continuity and insulation; microsectioning examines internal structure. One result should not be presented as proof of another.

What Should You Check After Reflow or Depaneling?

A room-temperature bare-board check is not the same as an assembled-board assessment. During reflow, the board becomes less stiff and materials expand at different rates. Components, solder, edge supports and fixtures add loads that are outside the basic bare-board bow-and-twist method. After cooling, some deformation recovers and some may remain.

When failure appears only after assembly, compare incoming flatness, panel location, paste printing, reflow profile, support-pin layout, component distribution and depaneling method. Measure the board both free and in its intended fixture if the product relies on mounting force. Record which condition produces the functional problem.

For a connector or thermal interface, inspect the actual local zone rather than averaging the entire board. For BGA-related opens, separate PCB shape from package warpage, paste volume and pad design before changing the fabrication limit.

What Information Should You Send for a Flatness-Critical PCB Order?

Send the fabrication files and a controlled drawing that identifies the critical flatness requirement. A complete manufacturing package includes:

  • Finished board dimensions, outline and panel preference
  • Layer count, proposed stack-up, copper weights and finished thickness
  • Material system and any mixed-material or stiffener construction
  • Maximum bow and twist, controlling method and sample state
  • Local coplanarity area, datum, maximum deviation and inspection method
  • Assembly process, peak thermal exposure and fixture constraints
  • Critical components, connectors, heat spreaders and enclosure interfaces
  • Required report format, sample size and lot traceability

At EBest Circuit (Best Technology), we will review the requirement against the actual board construction instead of treating one percentage as universal. Send your files and target PCB surface flatness criteria to sales@bestpcbs.com. We can align the drawing, manufacturing plan and assembly risk before production planning.

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PCB Test Coupons: Types, Testing & IPC Guide

September 17th, 2026

PCB test coupons are representative test structures placed on the same fabrication panel as the production boards. They are built with the same materials, copper plating, lamination, drilling, and other key processes so manufacturers can verify characteristics such as controlled impedance, plated-hole quality, via reliability, registration, and solderability without cutting into the finished PCB.

Different PCB test coupons serve different purposes. Impedance coupons are commonly checked with TDR, while structural coupons can be microsectioned to inspect plating and internal alignment. The coupon design should reflect the actual production stackup and fabrication process.

PCB test coupons integrated into the panel rail of a production PCB panel

What Is a PCB Test Coupon?

A PCB test coupon is a dedicated test structure manufactured on the same panel as the production PCB to represent selected features of the finished board.

Unlike the functional PCB, the coupon is created specifically for inspection or measurement. Depending on the requirement, it may reproduce:

  • Controlled-impedance traces
  • Plated through holes
  • Microvias or blind vias
  • Internal layer registration features
  • Copper plating structures
  • Solderability features

The key point is representation. A useful coupon should experience the same relevant fabrication processes as the board it is intended to represent.

PCB test coupons are commonly placed in the panel rail or other non-product area, so testing does not consume a usable PCB.

At EBest Circuit, coupon requirements can be reviewed together with the production stackup during DFM. For controlled-impedance, HDI, RF, or high-reliability boards, this helps keep the test structure aligned with the actual PCB manufacturing conditions.

Why Are Test Coupons Used Instead of Testing the Production PCB?

PCB test coupons allow measurements and destructive inspections to be performed without damaging the production board.

Some verification methods cannot be carried out conveniently on a finished PCB. Microsection analysis, for example, requires the sample to be cut, mounted, polished, and inspected under magnification.

Coupons also provide a more consistent structure for tests such as TDR because production routing may contain:

  • Vias
  • Pads
  • Connectors
  • BGA breakouts
  • Plane changes
  • Short trace segments

These features can make measurement results harder to interpret.

A dedicated coupon can reproduce the required stackup and trace geometry while providing enough length and accessible test points for repeatable measurement.

The coupon therefore does not replace electrical or functional testing of the PCB. It provides process evidence for specific fabrication characteristics.

What Types of PCB Test Coupons Are Commonly Used?

PCB test coupon types are usually selected according to what needs to be verified rather than by using one universal coupon design.

Coupon / Test Structure What It Checks Typical Test Method
Impedance coupon Single-ended or differential impedance TDR
PTH structural coupon Hole wall plating and registration Microsection
Via reliability coupon Via or interconnect integrity Thermal stress / resistance monitoring
Microvia coupon HDI microvia quality and stacking Microsection / reliability test
Solderability coupon Solder wetting performance Solderability test
Peel-strength coupon Copper adhesion Peel test
SIR coupon Surface insulation resistance Electrical resistance testing

Some IPC qualification and conformance structures use letter-based coupon designations. However, for most PCB buyers and engineers, the more useful question is not the letter itself but what manufacturing characteristic the coupon is intended to verify.

Common PCB test coupon types including impedance plated through-hole microvia via reliability solderability and SIR coupons

What Can PCB Test Coupons Verify?

PCB test coupons can verify several manufacturing characteristics that are difficult to confirm from visual inspection alone.

Common checks include:

  • Controlled impedance
  • Copper plating thickness
  • Plated through-hole integrity
  • Microvia quality
  • Annular ring condition
  • Internal layer registration
  • Solderability
  • Copper adhesion
  • Interconnect reliability

For example, an impedance coupon can confirm whether a nominal 50 Ω or 100 Ω structure is within tolerance after lamination, plating, and etching.

A microsection coupon serves a different purpose. It allows the manufacturer to inspect the actual cross-section of a plated hole or via and evaluate conditions such as copper distribution, registration, and interface quality.

PCB test coupon illustrating impedance trace geometry plating via quality and layer registration verification

Where Are Test Coupons Located on a PCB Panel?

PCB test coupons are usually placed in the panel rail or another non-functional area of the production panel.

This position allows the coupon to travel through the same major fabrication processes as the PCBs while remaining separate from the customer’s usable board outline.

A useful coupon should be positioned so that it represents the production process as closely as practical, especially for:

  • Lamination
  • Drilling
  • Copper plating
  • Etching
  • Surface treatment

Coupon placement also needs to leave enough room for test access, sectioning, or removal from the panel.

For controlled-impedance production, the coupon is typically designed around the same layer pair, dielectric thickness, copper condition, and trace geometry used by the actual impedance-controlled routing.

PCB panel showing test coupons located in the top and bottom panel rails

How Are Impedance Test Coupons Tested with TDR?

An impedance test coupon reproduces the controlled-impedance structure of the production PCB so its characteristic impedance can be measured with time-domain reflectometry, or TDR.

The coupon normally represents the same:

  • Signal layer
  • Reference plane
  • Dielectric thickness
  • Copper thickness
  • Trace width
  • Differential spacing, where applicable
  • Material system

During TDR testing, a fast electrical edge is launched into the coupon. The instrument measures reflections along the transmission line and converts them into an impedance profile.

The result is then compared with the specified target, such as:

  • 50 Ω single-ended
  • 90 Ω differential
  • 100 Ω differential

A typical tolerance may be ±10%, although tighter limits can be specified.

The coupon should be based on the final production stackup rather than only the original CAD trace width. Plating, etching, dielectric thickness, and manufacturing compensation can all change the finished impedance.

PCB impedance test coupon connected to TDR equipment for controlled impedance verification

How Are Test Coupons Used for Microsection and Via Inspection?

Microsection coupons are cut and polished so the internal PCB structure can be inspected directly under magnification.

This method is commonly used to evaluate plated through holes, blind vias, microvias, and multilayer registration.

A typical microsection can reveal:

  • Hole-wall copper thickness
  • Copper distribution
  • Annular ring condition
  • Layer-to-hole registration
  • Resin condition
  • Via interfaces
  • Microvia geometry
  • Lamination quality

Because the coupon is intentionally sacrificed, the production PCB remains intact.

For HDI boards, microsection inspection is especially useful because microvias, stacked structures, and thin dielectric layers can create manufacturing risks that are not visible from the board surface.

Microsection results should be interpreted against the relevant drawing, customer specification, and applicable IPC acceptance requirements rather than treated as a generic pass/fail image.

PCB microsection showing plated through hole microvia copper layers annular ring and resin

Who Should Design PCB Test Coupons—the Designer or the Fabricator?

PCB test coupon design is typically a shared responsibility: the PCB designer defines the electrical and reliability requirements, while the fabricator finalizes the coupon structure for the actual production process.

The customer should provide requirements such as:

  • Target impedance
  • Impedance tolerance
  • Stackup constraints
  • Material requirement
  • Via structure
  • Reliability requirement
  • Required reports or inspection records

The fabricator then knows the actual production details, including dielectric availability, drill size, finished copper thickness, plating allowance, and etching compensation.

For that reason, it is often better for the PCB manufacturer to create or adjust the coupon after the production stackup is confirmed.

If a customer-supplied coupon is included in the fabrication data, it should still be reviewed during DFM to make sure it matches the manufacturing stackup and test method.

Engineer reviewing PCB stackup impedance and test coupon requirements during DFM

What Test Coupon Requirements Should You Include in Your PCB RFQ?

A PCB RFQ should clearly state what needs to be verified rather than simply asking for “test coupons.”

For controlled-impedance or high-reliability projects, provide:

  • Gerber or ODB++ files
  • PCB stackup or stackup constraints
  • Material grade
  • Finished board thickness
  • Copper weight
  • Target impedance
  • Single-ended or differential requirement
  • Impedance tolerance
  • Critical routing layers
  • Via or microvia structure
  • Required test reports
  • Whether physical coupons should be returned

For example, “50 Ω controlled impedance required” is less useful than specifying the routing layer, reference plane, stackup requirement, and tolerance.

FAQ About PCB Test Coupons

1. Is a PCB test coupon part of the finished PCB? No. It is normally placed in the panel rail or another non-product area and removed from the production panel.

2. Do I need to include a test coupon in my Gerber files? Not always. In many projects, the customer provides the test requirement and the PCB manufacturer creates the coupon based on the final production stackup.

3. What is an impedance test coupon? It is a representative transmission-line structure used to measure the finished PCB impedance, commonly with TDR.

4. Can a test coupon prove that every PCB on the panel is good? No. A coupon provides representative process evidence for specific characteristics. It does not replace board-level inspection or electrical testing.

5. Are PCB test coupons normally sent to the customer? They can be. Whether physical coupons, TDR reports, microsection images, or other records are supplied should be defined in the order or quality requirement.

6. What information should I provide for controlled-impedance coupon testing? Provide the target impedance, tolerance, routing layer, reference plane, stackup, material, copper weight, and any special coupon or reporting requirements.

Ready to Review Your PCB Test Coupon Requirements?

PCB test coupons are most useful when they are tied to a specific manufacturing risk, whether that is impedance, plating, microvia quality, registration, or another measurable characteristic. Defining the test requirement before production makes the coupon more representative and the resulting data more useful.

EBest Circuit supports controlled-impedance, HDI, RF, multilayer PCB manufacturing, PCBA, DFM review, TDR testing, and microsection inspection. For projects that require coupon-based verification, send your Gerber files and PCB specifications to sales@bestpcbs.com. Our engineering team can review the stackup, test requirements, and coupon approach before fabrication.

After coupon results are approved, our SMT assembly workflow can also coordinate circuit board stencil requirements with the released fabrication data.

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